Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2022-02-16 | target/riscv: Add XVentanaCondOps custom extension | Philipp Tomsich | 1 | -0/+1 |
2022-01-21 | target/riscv: Support start kernel directly by KVM | Yifei Jiang | 1 | -1/+1 |
2022-01-21 | target/riscv: Add target/riscv/kvm.c to place the public kvm interface | Yifei Jiang | 1 | -0/+1 |
2022-01-08 | target/riscv: support for 128-bit M extension | Frédéric Pétrot | 1 | -0/+1 |
2021-06-08 | target/riscv: rvb: generalized reverse | Frank Chang | 1 | -0/+1 |
2021-05-11 | target/riscv: Consolidate RV32/64 16-bit instructions | Alistair Francis | 1 | -8/+3 |
2021-05-11 | target/riscv: Consolidate RV32/64 32-bit instructions | Alistair Francis | 1 | -1/+1 |
2021-03-04 | target-riscv: support QMP dump-guest-memory | Yifei Jiang | 1 | -0/+1 |
2020-11-03 | target/riscv: Add basic vmstate description of CPU | Yifei Jiang | 1 | -1/+2 |
2020-08-21 | meson: target | Paolo Bonzini | 1 | -0/+34 |