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AgeCommit message (Expand)AuthorFilesLines
2023-05-18target/riscv: Fix itrigger when icount is usedLIU Zhiwei1-0/+6
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu1-2/+4
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-1/+2
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+16
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen1-0/+3
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen1-0/+12
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen1-0/+5
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson3-0/+8
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo1-6/+2
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis1-2/+10
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD1-2/+5
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD1-0/+6
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD1-0/+17
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD1-4/+8
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD1-1/+2
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD1-2/+11
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD1-0/+6
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-1/+2
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD1-0/+27
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li1-6/+12
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD1-27/+31
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li1-0/+58
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li1-0/+53
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li1-0/+100
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li1-0/+55
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li1-0/+54
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li1-0/+71
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li1-0/+18
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li1-2/+2
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-12/+82
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li1-11/+6
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li1-5/+3
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau1-2/+2
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen1-0/+5
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li1-95/+237
2022-03-03target/riscv: add support for zdinxWeiwei Li1-78/+207
2022-03-03target/riscv: add support for zfinxWeiwei Li1-96/+218
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich1-4/+4
2022-02-16target/riscv: add support for svinval extensionWeiwei Li1-0/+75
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich1-0/+39
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich1-4/+4
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich3-55/+97
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei4-56/+9
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei1-4/+8
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