riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-06-10	target/riscv: add support for zmmul extension v0.1	Weiwei Li	1	-6/+12
2022-01-08	target/riscv: support for 128-bit M extension	Frédéric Pétrot	1	-13/+169
2022-01-08	target/riscv: support for 128-bit arithmetic instructions	Frédéric Pétrot	1	-13/+13
2021-10-22	target/riscv: Use gen_arith_per_ol for RVM	Richard Henderson	1	-3/+23
2021-10-22	target/riscv: Replace DisasContext.w with DisasContext.ol	Richard Henderson	1	-5/+5
2021-09-01	target/riscv: Move gen_* helpers for RVM	Richard Henderson	1	-0/+127
2021-09-01	target/riscv: Use gen_arith for mulh and mulhu	Richard Henderson	1	-22/+18
2021-09-01	target/riscv: Remove gen_arith_div*	Richard Henderson	1	-8/+8
2021-09-01	target/riscv: Add DisasExtend to gen_arith*	Richard Henderson	1	-8/+8
2021-09-01	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	Richard Henderson	1	-6/+6
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	1	-2/+10
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-0/+120