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path: root/target/riscv/insn_trans/trans_rvb.c.inc
AgeCommit message (Expand)AuthorFilesLines
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li1-0/+18
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li1-2/+2
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-12/+82
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich1-4/+4
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich1-4/+4
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot1-10/+10
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot1-11/+11
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot1-3/+3
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson1-40/+52
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson1-17/+16
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson1-1/+6
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson1-4/+4
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich1-5/+8
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich1-72/+14
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich1-32/+8
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich1-22/+17
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich1-22/+29
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich1-1/+31
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich1-10/+15
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich1-70/+0
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich1-56/+0
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich1-5/+11
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich1-3/+5
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich1-1/+1
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich1-2/+4
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson1-13/+6
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson1-70/+59
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson1-15/+9
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson1-0/+234
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson1-15/+15
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson1-2/+2
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+26
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+24
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+26
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+31
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+39
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+52
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+97
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng1-0/+12
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng1-0/+24
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+32
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng1-0/+18
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+13
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+44
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