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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)AuthorFilesLines
2021-12-20target/riscv: zfh: half-precision floating-point compareKito Cheng1-0/+3
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng1-0/+19
2021-12-20target/riscv: zfh: half-precision computationalKito Cheng1-0/+11
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng1-0/+4
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich1-4/+0
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich1-5/+7
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich1-5/+7
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich1-5/+1
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich1-19/+21
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich1-0/+5
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich1-8/+9
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich1-8/+0
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich1-7/+0
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich1-8/+12
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson1-0/+1
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+3
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+6
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+4
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+4
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+6
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+8
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+17
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng1-0/+3
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng1-0/+4
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+6
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng1-0/+3
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+2
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-1/+10
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng1-5/+5
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-1/+66
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+11
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+6
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei1-0/+3
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: integer extract instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+1
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+3
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei1-0/+1
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei1-0/+2
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei1-0/+8
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei1-0/+5
generated by cgit v1.1 at 2024-12-28 00:23:28 +0000