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authorKito Cheng <kito.cheng@sifive.com>2021-05-06 00:06:07 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-06-08 09:59:44 +1000
commit82655d8115f022a0132a74e0229dc7fa9b623b87 (patch)
tree566083ec36dd820d3a68861062099543095897fe /target/riscv/insn32.decode
parent6ef5843182382f6a84995590ad91047b0f2bc1fa (diff)
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target/riscv: rvb: min/max instructions
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
-rw-r--r--target/riscv/insn32.decode4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9b2fd4b..81dfdfb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -669,6 +669,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2