riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-02-16	target/riscv: add support for svinval extension	Weiwei Li	1	-0/+7
2022-01-08	target/riscv: support for 128-bit M extension	Frédéric Pétrot	1	-0/+7
2022-01-08	target/riscv: support for 128-bit arithmetic instructions	Frédéric Pétrot	1	-0/+3
2022-01-08	target/riscv: support for 128-bit shift instructions	Frédéric Pétrot	1	-0/+10
2022-01-08	target/riscv: accessors to registers upper part and 128-bit load/store	Frédéric Pétrot	1	-0/+5
2021-12-20	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...	Frank Chang	1	-2/+2
2021-12-20	target/riscv: rvv-1.0: add vector unit-stride mask load/store insns	Frank Chang	1	-0/+4
2021-12-20	target/riscv: rvv-1.0: add vsetivli instruction	Frank Chang	1	-0/+2
2021-12-20	target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11	Frank Chang	1	-2/+2
2021-12-20	target/riscv: rvv-1.0: floating-point reciprocal estimate instruction	Frank Chang	1	-0/+1
2021-12-20	target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...	Frank Chang	1	-0/+1
2021-12-20	target/riscv: rvv-1.0: narrowing floating-point/integer type-convert	Frank Chang	1	-5/+10
2021-12-20	target/riscv: rvv-1.0: widening floating-point/integer type-convert	Frank Chang	1	-5/+8
2021-12-20	target/riscv: rvv-1.0: floating-point/integer type-convert instructions	Frank Chang	1	-4/+7
2021-12-20	target/riscv: rvv-1.0: remove integer extract instruction	Frank Chang	1	-1/+0
2021-12-20	target/riscv: rvv-1.0: remove vmford.vv and vmford.vf	Frank Chang	1	-2/+0
2021-12-20	target/riscv: rvv-1.0: remove widening saturating scaled multiply-add	Frank Chang	1	-7/+0
2021-12-20	target/riscv: rvv-1.0: narrowing fixed-point clip instructions	Frank Chang	1	-6/+6
2021-12-20	target/riscv: rvv-1.0: floating-point slide instructions	Frank Chang	1	-0/+2
2021-12-20	target/riscv: rvv-1.0: widening integer multiply-add instructions	Frank Chang	1	-3/+3
2021-12-20	target/riscv: rvv-1.0: narrowing integer right shift instructions	Frank Chang	1	-6/+6
2021-12-20	target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow	Frank Chang	1	-10/+10
2021-12-20	target/riscv: rvv-1.0: single-width averaging add and subtract instructions	Frank Chang	1	-5/+8
2021-12-20	target/riscv: rvv-1.0: integer extension instructions	Frank Chang	1	-0/+8
2021-12-20	target/riscv: rvv-1.0: whole register move instructions	Frank Chang	1	-0/+4
2021-12-20	target/riscv: rvv-1.0: floating-point scalar move instructions	Frank Chang	1	-2/+2
2021-12-20	target/riscv: rvv-1.0: integer scalar move instructions	Frank Chang	1	-1/+2
2021-12-20	target/riscv: rvv-1.0: register gather instructions	Frank Chang	1	-0/+1
2021-12-20	target/riscv: rvv-1.0: element index instruction	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: iota instruction	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: set-X-first mask bit instructions	Frank Chang	1	-3/+3
2021-12-20	target/riscv: rvv-1.0: find-first-set mask bit instruction	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: count population in mask instruction	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: floating-point classify instructions	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: floating-point square-root instruction	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: load/store whole register instructions	Frank Chang	1	-0/+22
2021-12-20	target/riscv: rvv-1.0: fault-only-first unit stride load	Frank Chang	1	-8/+6
2021-12-20	target/riscv: rvv-1.0: index load and store instructions	Frank Chang	1	-11/+10
2021-12-20	target/riscv: rvv-1.0: stride load and store instructions	Frank Chang	1	-23/+20
2021-12-20	target/riscv: rvv-1.0: remove amo operations instructions	Frank Chang	1	-24/+0
2021-12-20	target/riscv: zfh: half-precision floating-point classify	Kito Cheng	1	-0/+1
2021-12-20	target/riscv: zfh: half-precision floating-point compare	Kito Cheng	1	-0/+3
2021-12-20	target/riscv: zfh: half-precision convert and move	Kito Cheng	1	-0/+19
2021-12-20	target/riscv: zfh: half-precision computational	Kito Cheng	1	-0/+11
2021-12-20	target/riscv: zfh: half-precision load and store	Kito Cheng	1	-0/+4
2021-10-07	target/riscv: Remove RVB (replaced by Zb[abcs])	Philipp Tomsich	1	-4/+0
2021-10-07	target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh	Philipp Tomsich	1	-5/+7
2021-10-07	target/riscv: Add rev8 instruction, removing grev/grevi	Philipp Tomsich	1	-5/+7
2021-10-07	target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci	Philipp Tomsich	1	-5/+1
2021-10-07	target/riscv: Reassign instructions to the Zbb-extension	Philipp Tomsich	1	-19/+21