riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson	1	-3/+7
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann	1	-1/+2
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann	1	-1/+2
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann	1	-0/+15
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann	1	-0/+28
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann	1	-0/+35
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann	1	-0/+17
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann	1	-0/+10
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann	1	-0/+8
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann	1	-0/+2
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann	1	-0/+25
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann	1	-0/+10
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann	1	-0/+19
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann	1	-0/+30