index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
/
insn32.decode
Age
Commit message (
Expand
)
Author
Files
Lines
2022-09-27
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
Yang Liu
1
-2
/
+4
2022-09-07
target/riscv: Add Zihintpause support
Dao Lu
1
-1
/
+6
2022-04-29
target/riscv: rvk: add support for zksed/zksh extension
Weiwei Li
1
-0
/
+6
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...
Weiwei Li
1
-0
/
+5
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...
Weiwei Li
1
-0
/
+6
2022-04-29
target/riscv: rvk: add support for sha256 related instructions in zknh extension
Weiwei Li
1
-0
/
+5
2022-04-29
target/riscv: rvk: add support for zkne/zknd extension in RV64
Weiwei Li
1
-0
/
+12
2022-04-29
target/riscv: rvk: add support for zknd/zkne extension in RV32
Weiwei Li
1
-0
/
+11
2022-04-29
target/riscv: rvk: add support for zbkx extension
Weiwei Li
1
-0
/
+4
2022-04-29
target/riscv: rvk: add support for zbkc extension
Weiwei Li
1
-1
/
+2
2022-04-29
target/riscv: rvk: add support for zbkb extension
Weiwei Li
1
-16
/
+29
2022-02-16
target/riscv: add support for svinval extension
Weiwei Li
1
-0
/
+7
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
1
-0
/
+7
2022-01-08
target/riscv: support for 128-bit arithmetic instructions
Frédéric Pétrot
1
-0
/
+3
2022-01-08
target/riscv: support for 128-bit shift instructions
Frédéric Pétrot
1
-0
/
+10
2022-01-08
target/riscv: accessors to registers upper part and 128-bit load/store
Frédéric Pétrot
1
-0
/
+5
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
1
-0
/
+4
2021-12-20
target/riscv: rvv-1.0: add vsetivli instruction
Frank Chang
1
-0
/
+2
2021-12-20
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
1
-5
/
+10
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
1
-5
/
+8
2021-12-20
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
Frank Chang
1
-4
/
+7
2021-12-20
target/riscv: rvv-1.0: remove integer extract instruction
Frank Chang
1
-1
/
+0
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
1
-2
/
+0
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
1
-7
/
+0
2021-12-20
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
Frank Chang
1
-6
/
+6
2021-12-20
target/riscv: rvv-1.0: floating-point slide instructions
Frank Chang
1
-0
/
+2
2021-12-20
target/riscv: rvv-1.0: widening integer multiply-add instructions
Frank Chang
1
-3
/
+3
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
1
-6
/
+6
2021-12-20
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
Frank Chang
1
-10
/
+10
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
1
-5
/
+8
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
1
-0
/
+8
2021-12-20
target/riscv: rvv-1.0: whole register move instructions
Frank Chang
1
-0
/
+4
2021-12-20
target/riscv: rvv-1.0: floating-point scalar move instructions
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: integer scalar move instructions
Frank Chang
1
-1
/
+2
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: rvv-1.0: element index instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: iota instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: set-X-first mask bit instructions
Frank Chang
1
-3
/
+3
2021-12-20
target/riscv: rvv-1.0: find-first-set mask bit instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: count population in mask instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: floating-point classify instructions
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: floating-point square-root instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: load/store whole register instructions
Frank Chang
1
-0
/
+22
2021-12-20
target/riscv: rvv-1.0: fault-only-first unit stride load
Frank Chang
1
-8
/
+6
2021-12-20
target/riscv: rvv-1.0: index load and store instructions
Frank Chang
1
-11
/
+10
2021-12-20
target/riscv: rvv-1.0: stride load and store instructions
Frank Chang
1
-23
/
+20
[next]