riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-05-05	target/riscv: add support for Zcmt extension	Weiwei Li	1	-1/+6
2023-05-05	target/riscv: add support for Zcmp extension	Weiwei Li	1	-0/+18
2023-05-05	target/riscv: add support for Zcb extension	Weiwei Li	1	-0/+23
2023-05-05	target/riscv: add support for Zcd extension	Weiwei Li	1	-4/+4
2023-05-05	target/riscv: add support for Zcf extension	Weiwei Li	1	-4/+4
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot	1	-3/+4
2022-01-08	target/riscv: accessors to registers upper part and 128-bit load/store	Frédéric Pétrot	1	-4/+23
2021-05-11	target/riscv: Consolidate RV32/64 16-bit instructions	Alistair Francis	1	-0/+30
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson	1	-1/+6
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson	1	-32/+3
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson	1	-6/+23
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson	1	-6/+6
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson	1	-37/+47
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann	1	-0/+31
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann	1	-0/+43
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann	1	-0/+55