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path: root/target/riscv/helper.h
AgeCommit message (Expand)AuthorFilesLines
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou1-0/+4
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov1-0/+3
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter1-0/+3
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk1-0/+6
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov1-0/+14
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood1-0/+62
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter1-0/+6
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner1-0/+19
2023-07-10target/riscv: Add support for Zvfbfwma extensionWeiwei Li1-0/+3
2023-07-10target/riscv: Add support for Zvfbfmin extensionWeiwei Li1-0/+3
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li1-0/+4
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-2/+10
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li1-0/+3
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+2
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+3
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-0/+1
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson1-1/+0
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson1-0/+1
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-0/+2
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu1-5/+10
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li1-0/+3
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li1-0/+8
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li1-0/+6
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li1-0/+2
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li1-0/+3
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li1-4/+1
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li1-1/+1
2022-03-03target/riscv: add support for zfinxWeiwei Li1-1/+1
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei1-2/+2
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+3
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-0/+6
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang1-0/+5
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang1-10/+12
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang1-0/+1
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang1-6/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang1-22/+0
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang1-0/+7
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang1-0/+16
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang1-0/+14
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang1-0/+4
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang1-0/+21
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