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helper.h
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Author
Files
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2022-09-27
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
Yang Liu
1
-5
/
+10
2022-04-29
target/riscv: rvk: add support for zksed/zksh extension
Weiwei Li
1
-0
/
+3
2022-04-29
target/riscv: rvk: add support for zkne/zknd extension in RV64
Weiwei Li
1
-0
/
+8
2022-04-29
target/riscv: rvk: add support for zknd/zkne extension in RV32
Weiwei Li
1
-0
/
+6
2022-04-29
target/riscv: rvk: add support for zbkx extension
Weiwei Li
1
-0
/
+2
2022-04-29
target/riscv: rvk: add support for zbkb extension
Weiwei Li
1
-0
/
+3
2022-04-22
target/riscv: optimize helper for vmv<nr>r.v
Weiwei Li
1
-4
/
+1
2022-03-03
target/riscv: add support for zhinx/zhinxmin
Weiwei Li
1
-1
/
+1
2022-03-03
target/riscv: add support for zfinx
Weiwei Li
1
-1
/
+1
2022-01-21
target/riscv: Don't save pc when exception return
LIU Zhiwei
1
-2
/
+2
2022-01-08
target/riscv: helper functions to wrap calls to 128-bit csr insns
Frédéric Pétrot
1
-0
/
+3
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
1
-0
/
+6
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
1
-0
/
+2
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
1
-0
/
+4
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
1
-0
/
+4
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
1
-0
/
+5
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
1
-10
/
+12
2021-12-20
target/riscv: add "set round to odd" rounding mode helper function
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
1
-0
/
+2
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
1
-6
/
+0
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
1
-22
/
+0
2021-12-20
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
Frank Chang
1
-12
/
+12
2021-12-20
target/riscv: rvv-1.0: floating-point slide instructions
Frank Chang
1
-0
/
+7
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
1
-12
/
+12
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
1
-0
/
+16
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
1
-0
/
+14
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
1
-0
/
+4
2021-12-20
target/riscv: rvv-1.0: find-first-set mask bit instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: count population in mask instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: load/store whole register instructions
Frank Chang
1
-0
/
+21
2021-12-20
target/riscv: rvv-1.0: fault-only-first unit stride load
Frank Chang
1
-22
/
+4
2021-12-20
target/riscv: rvv-1.0: index load and store instructions
Frank Chang
1
-35
/
+32
2021-12-20
target/riscv: rvv-1.0: stride load and store instructions
Frank Chang
1
-105
/
+24
2021-12-20
target/riscv: rvv-1.0: remove amo operations instructions
Frank Chang
1
-27
/
+0
2021-12-20
target/riscv: zfh: half-precision floating-point classify
Kito Cheng
1
-0
/
+1
2021-12-20
target/riscv: zfh: half-precision floating-point compare
Kito Cheng
1
-0
/
+3
2021-12-20
target/riscv: zfh: half-precision convert and move
Kito Cheng
1
-0
/
+12
2021-12-20
target/riscv: zfh: half-precision computational
Kito Cheng
1
-0
/
+13
2021-10-07
target/riscv: Add rev8 instruction, removing grev/grevi
Philipp Tomsich
1
-2
/
+0
2021-10-07
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Philipp Tomsich
1
-2
/
+0
2021-10-07
target/riscv: Add instructions of the Zbc-extension
Philipp Tomsich
1
-0
/
+2
2021-09-01
target/riscv: Reorg csr instructions
Richard Henderson
1
-3
/
+3
2021-06-08
target/riscv: rvb: generalized or-combine
Frank Chang
1
-0
/
+2
2021-06-08
target/riscv: rvb: generalized reverse
Frank Chang
1
-0
/
+4
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
1
-10
/
+8
2020-12-17
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
1
-16
/
+8
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
1
-1
/
+2
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
1
-2
/
+0
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
1
-0
/
+1
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