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path: root/target/riscv/gdbstub.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza1-1/+1
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li1-1/+1
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-1/+2
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li1-2/+2
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée1-0/+1
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng1-75/+0
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng1-0/+9
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng1-3/+6
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng1-2/+2
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng1-0/+3
2022-09-27target/riscv: Check the correct exception cause in vector GDB stubFrank Chang1-2/+2
2022-09-27target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess1-30/+2
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot1-0/+3
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei1-19/+52
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot1-0/+5
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang1-0/+184
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-1/+1
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-4/+4
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng1-1/+1
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-4/+4
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng1-264/+44
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-10/+10
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis1-5/+6
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard1-9/+11
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens1-0/+9
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens1-0/+23
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens1-2/+2
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic1-2/+4
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson1-11/+339
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark1-2/+8
2018-03-07RISC-V GDB StubMichael Clark1-0/+62
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