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gdbstub.c
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Author
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2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
1
-1
/
+1
2021-10-22
target/riscv: Split misa.mxl and misa.ext
Richard Henderson
1
-4
/
+4
2021-06-24
target/riscv: gdbstub: Fix dynamic CSR XML generation
Bin Meng
1
-1
/
+1
2021-05-11
target/riscv: Use RISCVException enum for CSR access
Alistair Francis
1
-4
/
+4
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
1
-264
/
+44
2020-03-17
gdbstub: extend GByteArray to read register helpers
Alex Bennée
1
-10
/
+10
2020-02-27
target/riscv: Add the Hypervisor CSRs to CPUState
Alistair Francis
1
-5
/
+6
2020-02-10
riscv: Separate FPU register size from core register size in gdbstub [v2]
Keith Packard
1
-9
/
+11
2019-10-28
target/riscv: Make the priv register writable by GDB
Jonathan Behrens
1
-0
/
+9
2019-10-28
target/riscv: Expose "priv" register for GDB for reads
Jonathan Behrens
1
-0
/
+23
2019-10-28
target/riscv: Tell gdbstub the correct number of CSRs
Jonathan Behrens
1
-2
/
+2
2019-09-17
gdbstub: riscv: fix the fflags registers
KONRAD Frederic
1
-2
/
+4
2019-06-12
Include qemu-common.h exactly where needed
Markus Armbruster
1
-1
/
+0
2019-03-19
RISC-V: Add hooks to use the gdb xml files.
Jim Wilson
1
-11
/
+339
2019-01-08
RISC-V: Implement modular CSR helper interface
Michael Clark
1
-2
/
+8
2018-03-07
RISC-V GDB Stub
Michael Clark
1
-0
/
+62