riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-05-05	target/riscv: Use PRV_RESERVED instead of PRV_H	Weiwei Li	1	-1/+1
2023-05-05	target/riscv: Fix lines with over 80 characters	Weiwei Li	1	-1/+2
2023-05-05	target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig	Weiwei Li	1	-2/+2
2023-03-07	gdbstub: move register helpers into standalone include	Alex Bennée	1	-0/+1
2023-03-01	target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml	Bin Meng	1	-75/+0
2023-03-01	target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()	Bin Meng	1	-0/+9
2023-03-01	target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled	Bin Meng	1	-3/+6
2023-03-01	target/riscv: gdbstub: Minor change for better readability	Bin Meng	1	-2/+2
2023-03-01	target/riscv: gdbstub: Check priv spec version before reporting CSR	Bin Meng	1	-0/+3
2022-09-27	target/riscv: Check the correct exception cause in vector GDB stub	Frank Chang	1	-2/+2
2022-09-27	target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml	Andrew Burgess	1	-30/+2
2022-02-16	target/riscv: correct "code should not be reached" for x-rv128	Frédéric Pétrot	1	-0/+3
2022-01-21	target/riscv: Use gdb xml according to max mxlen	LIU Zhiwei	1	-19/+52
2022-01-08	target/riscv: setup everything for rv64 to support rv128 execution	Frédéric Pétrot	1	-0/+5
2021-12-20	target/riscv: gdb: support vector registers for rv64 & rv32	Hsiangkai Wang	1	-0/+184
2021-10-22	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	Richard Henderson	1	-1/+1
2021-10-22	target/riscv: Split misa.mxl and misa.ext	Richard Henderson	1	-4/+4
2021-06-24	target/riscv: gdbstub: Fix dynamic CSR XML generation	Bin Meng	1	-1/+1
2021-05-11	target/riscv: Use RISCVException enum for CSR access	Alistair Francis	1	-4/+4
2021-01-16	target/riscv: Generate the GDB XML file for CSR registers dynamically	Bin Meng	1	-264/+44
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée	1	-10/+10
2020-02-27	target/riscv: Add the Hypervisor CSRs to CPUState	Alistair Francis	1	-5/+6
2020-02-10	riscv: Separate FPU register size from core register size in gdbstub [v2]	Keith Packard	1	-9/+11
2019-10-28	target/riscv: Make the priv register writable by GDB	Jonathan Behrens	1	-0/+9
2019-10-28	target/riscv: Expose "priv" register for GDB for reads	Jonathan Behrens	1	-0/+23
2019-10-28	target/riscv: Tell gdbstub the correct number of CSRs	Jonathan Behrens	1	-2/+2
2019-09-17	gdbstub: riscv: fix the fflags registers	KONRAD Frederic	1	-2/+4
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	1	-11/+339
2019-01-08	RISC-V: Implement modular CSR helper interface	Michael Clark	1	-2/+8
2018-03-07	RISC-V GDB Stub	Michael Clark	1	-0/+62