riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-03-03	target/riscv: add support for zhinx/zhinxmin	Weiwei Li	1	-44/+45
2022-03-03	target/riscv: add support for zfinx	Weiwei Li	1	-44/+45
2021-12-20	target/riscv: add "set round to odd" rounding mode helper function	Frank Chang	1	-0/+5
2021-12-20	target/riscv: introduce floating-point rounding mode enum	Frank Chang	1	-6/+6
2021-12-20	target/riscv: zfh: half-precision floating-point classify	Kito Cheng	1	-0/+6
2021-12-20	target/riscv: zfh: half-precision floating-point compare	Kito Cheng	1	-0/+21
2021-12-20	target/riscv: zfh: half-precision convert and move	Kito Cheng	1	-0/+67
2021-12-20	target/riscv: zfh: half-precision computational	Kito Cheng	1	-0/+86
2021-10-29	target/riscv: change the api for RVF/RVD fmin/fmax	Chih-Min Chao	1	-4/+12
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	1	-8/+8
2020-12-17	target/riscv: fpu_helper: Match function defs in HELPER macros	Alistair Francis	1	-8/+0
2020-08-21	target/riscv: Check nanboxed inputs to fp helpers	Richard Henderson	1	-18/+46
2020-08-21	target/riscv: Generate nanboxed results from fp helpers	Richard Henderson	1	-19/+23
2020-07-02	target/riscv: vector floating-point classify instructions	LIU Zhiwei	1	-30/+3
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée	1	-0/+1
2019-02-11	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark	1	-3/+3
2018-12-20	Clean up includes	Markus Armbruster	1	-1/+0
2018-05-17	target/riscv: Remove floatX_maybe_silence_nan from conversions	Richard Henderson	1	-4/+2
2018-03-07	RISC-V FPU Support	Michael Clark	1	-0/+373