index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
/
debug.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-09-11
target/riscv: Allocate itrigger timers only once
Akihiko Odaki
1
-3
/
+12
2023-09-08
riscv: spelling fixes
Michael Tokarev
1
-5
/
+5
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
1
-5
/
+6
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
1
-5
/
+5
2023-02-07
target/riscv: set tval for triggered watchpoints
Sergey Matyukevich
1
-1
/
+0
2023-01-06
target/riscv: Add itrigger_enabled field to CPURISCVState
LIU Zhiwei
1
-0
/
+3
2023-01-06
target/riscv: Enable native debug itrigger
LIU Zhiwei
1
-0
/
+72
2023-01-06
target/riscv: Add itrigger support when icount is enabled
LIU Zhiwei
1
-0
/
+59
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
1
-0
/
+71
2022-12-14
cleanup: Tweak and re-run return_directly.cocci
Markus Armbruster
1
-4
/
+2
2022-09-27
target/riscv: debug: Add initial support of type 6 trigger
Frank Chang
1
-4
/
+170
2022-09-27
target/riscv: debug: Check VU/VS modes for type 2 trigger
Frank Chang
1
-0
/
+10
2022-09-27
target/riscv: debug: Create common trigger actions function
Frank Chang
1
-2
/
+57
2022-09-27
target/riscv: debug: Introduce tinfo CSR
Frank Chang
1
-3
/
+7
2022-09-27
target/riscv: debug: Restrict the range of tselect value can be written
Frank Chang
1
-6
/
+3
2022-09-27
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Frank Chang
1
-65
/
+38
2022-09-27
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
Frank Chang
1
-5
/
+10
2022-09-27
target/riscv: debug: Determine the trigger type from tdata1.type
Frank Chang
1
-55
/
+133
2022-06-10
target/riscv/debug.c: keep experimental rv128 support working
Frédéric Pétrot
1
-0
/
+2
2022-04-22
target/riscv: csr: Hook debug CSR read/write
Bin Meng
1
-0
/
+27
2022-04-22
target/riscv: debug: Implement debug related TCGCPUOps
Bin Meng
1
-0
/
+75
2022-04-22
target/riscv: Add initial support for the Sdtrig extension
Bin Meng
1
-0
/
+339