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path: root/target/riscv/debug.c
AgeCommit message (Expand)AuthorFilesLines
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki1-3/+12
2023-09-08riscv: spelling fixesMichael Tokarev1-5/+5
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-5/+6
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-5/+5
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich1-1/+0
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei1-0/+3
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei1-0/+72
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei1-0/+59
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-0/+71
2022-12-14cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster1-4/+2
2022-09-27target/riscv: debug: Add initial support of type 6 triggerFrank Chang1-4/+170
2022-09-27target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang1-0/+10
2022-09-27target/riscv: debug: Create common trigger actions functionFrank Chang1-2/+57
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang1-3/+7
2022-09-27target/riscv: debug: Restrict the range of tselect value can be writtenFrank Chang1-6/+3
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang1-65/+38
2022-09-27target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang1-5/+10
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang1-55/+133
2022-06-10target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot1-0/+2
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng1-0/+27
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng1-0/+75
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng1-0/+339