riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-07	target/riscv: set tval for triggered watchpoints	Sergey Matyukevich	1	-1/+0
2023-01-06	target/riscv: Add itrigger_enabled field to CPURISCVState	LIU Zhiwei	1	-0/+3
2023-01-06	target/riscv: Enable native debug itrigger	LIU Zhiwei	1	-0/+72
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei	1	-0/+59
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei	1	-0/+71
2022-12-14	cleanup: Tweak and re-run return_directly.cocci	Markus Armbruster	1	-4/+2
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang	1	-4/+170
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang	1	-0/+10
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang	1	-2/+57
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang	1	-3/+7
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang	1	-6/+3
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang	1	-65/+38
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang	1	-5/+10
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang	1	-55/+133
2022-06-10	target/riscv/debug.c: keep experimental rv128 support working	Frédéric Pétrot	1	-0/+2
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng	1	-0/+27
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng	1	-0/+75
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng	1	-0/+339