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cpu_helper.c
Age
Commit message (
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Author
Files
Lines
2023-07-10
target/riscv: Set the correct exception for implict G-stage translation fail
Jason Chien
1
-1
/
+0
2023-07-10
target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
Weiwei Li
1
-2
/
+5
2023-07-10
target/riscv: Add additional xlen for address when MPRV=1
Weiwei Li
1
-0
/
+1
2023-07-10
target/riscv: Make MPV only work when MPP != PRV_M
Weiwei Li
1
-1
/
+2
2023-06-26
target: Widen pc/cs_base in cpu_get_tb_cpu_state
Anton Johansson
1
-2
/
+2
2023-06-13
target/riscv: Fix initialized value for cur_pmmask
Weiwei Li
1
-2
/
+2
2023-06-13
target/riscv: Reuse tb->flags.FS
Mayuresh Chitale
1
-0
/
+6
2023-06-13
target/riscv: Change the return type of pmp_hart_has_privs() to bool
Weiwei Li
1
-4
/
+4
2023-06-13
target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
Weiwei Li
1
-10
/
+6
2023-06-13
target/riscv: Update pmp_get_tlb_size()
Weiwei Li
1
-5
/
+2
2023-06-05
tcg: Split out tcg/oversized-guest.h
Richard Henderson
1
-0
/
+1
2023-05-05
riscv: Make sure an exception is raised if a pte is malformed
Alexandre Ghiti
1
-4
/
+11
2023-05-05
target/riscv: Fix Guest Physical Address Translation
Irina Ryapolova
1
-9
/
+16
2023-05-05
target/riscv: Reorg sum check in get_physical_address
Richard Henderson
1
-11
/
+11
2023-05-05
target/riscv: Reorg access check in get_physical_address
Richard Henderson
1
-33
/
+36
2023-05-05
target/riscv: Merge checks for reserved pte flags
Richard Henderson
1
-6
/
+6
2023-05-05
target/riscv: Don't modify SUM with is_debug
Richard Henderson
1
-1
/
+1
2023-05-05
target/riscv: Suppress pte update with is_debug
Richard Henderson
1
-1
/
+1
2023-05-05
target/riscv: Move leaf pte processing out of level loop
Richard Henderson
1
-111
/
+123
2023-05-05
target/riscv: Hoist pbmte and hade out of the level loop
Richard Henderson
1
-8
/
+8
2023-05-05
target/riscv: Hoist second stage mode change to callers
Richard Henderson
1
-10
/
+2
2023-05-05
target/riscv: Check SUM in the correct register
Richard Henderson
1
-4
/
+8
2023-05-05
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Richard Henderson
1
-32
/
+17
2023-05-05
target/riscv: Move hstatus.spvp check to check_access_hlsv
Richard Henderson
1
-9
/
+1
2023-05-05
target/riscv: Introduce mmuidx_2stage
Richard Henderson
1
-14
/
+6
2023-05-05
target/riscv: Introduce mmuidx_priv
Richard Henderson
1
-5
/
+1
2023-05-05
target/riscv: Introduce mmuidx_sum
Richard Henderson
1
-1
/
+1
2023-05-05
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
Richard Henderson
1
-1
/
+1
2023-05-05
target/riscv: Handle HLV, HSV via helpers
Richard Henderson
1
-17
/
+9
2023-05-05
target/riscv: Reduce overhead of MSTATUS_SUM change
Fei Wu
1
-2
/
+15
2023-05-05
target/riscv: Separate priv from mmu_idx
Fei Wu
1
-1
/
+3
2023-05-05
target/riscv: Add a tb flags field for vstart
LIU Zhiwei
1
-0
/
+1
2023-05-05
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
Richard Henderson
1
-17
/
+16
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
1
-5
/
+6
2023-05-05
target/riscv: Extract virt enabled state from tb flags
LIU Zhiwei
1
-0
/
+1
2023-05-05
target/riscv: Legalize MPP value in write_mstatus
Weiwei Li
1
-6
/
+2
2023-05-05
target/riscv: Use PRV_RESERVED instead of PRV_H
Weiwei Li
1
-1
/
+1
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
1
-1
/
+2
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
1
-19
/
+38
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
1
-81
/
+82
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
1
-28
/
+23
2023-05-05
target/riscv: Fix addr type for get_physical_address
Weiwei Li
1
-2
/
+2
2023-05-05
target/riscv: Remove redundant parentheses
Weiwei Li
1
-1
/
+1
2023-05-05
target/riscv: Convert env->virt to a bool env->virt_enabled
LIU Zhiwei
1
-3
/
+3
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
Weiwei Li
1
-4
/
+1
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Weiwei Li
1
-4
/
+0
2023-05-05
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
Weiwei Li
1
-3
/
+1
2023-05-05
target/riscv: Simplify type conversion for CPURISCVState
Weiwei Li
1
-4
/
+4
2023-05-05
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Weiwei Li
1
-5
/
+4
2023-03-01
Merge patch series "target/riscv: Add support for Svadu extension"
Palmer Dabbelt
1
-2
/
+14
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