Age | Commit message (Expand) | Author | Files | Lines |
2023-02-07 | target/riscv: set tval for triggered watchpoints | Sergey Matyukevich | 1 | -0/+6 |
2023-02-07 | target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP | Anup Patel | 1 | -2/+0 |
2023-01-18 | bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx | Philippe Mathieu-Daudé | 1 | -5/+5 |
2023-01-06 | Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem... | Peter Maydell | 1 | -8/+18 |
2023-01-06 | target/riscv: support cache-related PMU events in virtual mode | Jim Shu | 1 | -1/+1 |
2023-01-06 | target/riscv: Add itrigger_enabled field to CPURISCVState | LIU Zhiwei | 1 | -2/+1 |
2023-01-06 | target/riscv: Add itrigger support when icount is enabled | LIU Zhiwei | 1 | -0/+3 |
2023-01-06 | target/riscv: Add itrigger support when icount is not enabled | LIU Zhiwei | 1 | -0/+6 |
2023-01-06 | target/riscv: Fix PMP propagation for tlb | LIU Zhiwei | 1 | -7/+9 |
2023-01-04 | target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip | Richard Henderson | 1 | -9/+1 |
2022-09-13 | target/riscv: Honour -semihosting-config userspace=on and enable=on | Peter Maydell | 1 | -6/+3 |
2022-09-07 | target/riscv: Add few cache related PMU events | Atish Patra | 1 | -0/+25 |
2022-09-07 | target/riscv: Add vstimecmp support | Atish Patra | 1 | -3/+8 |
2022-09-07 | target/riscv: Use official extension names for AIA CSRs | Anup Patel | 1 | -1/+2 |
2022-09-07 | target/riscv: rvv: Add mask agnostic for vv instructions | Yueh-Ting (eop) Chen | 1 | -0/+2 |
2022-09-07 | target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() | Anup Patel | 1 | -6/+246 |
2022-07-03 | target/riscv: Update default priority table for local interrupts | Anup Patel | 1 | -69/+65 |
2022-06-28 | semihosting: Return void from do_common_semihosting | Richard Henderson | 1 | -1/+1 |
2022-06-10 | target/riscv: rvv: Add tail agnostic for vv instructions | eopXD | 1 | -0/+2 |
2022-06-10 | target/riscv: Wake on VS-level external interrupts | Andrew Bresticker | 1 | -1/+1 |
2022-05-24 | target/riscv: Set [m|s]tval for both illegal and virtual instruction traps | Anup Patel | 1 | -0/+1 |
2022-05-24 | target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode | Anup Patel | 1 | -2/+1 |
2022-04-22 | hw/intc: Make RISC-V ACLINT mtime MMIO register writable | Frank Chang | 1 | -2/+2 |
2022-04-22 | target/riscv: Use cpu_loop_exit_restore directly from mmu faults | Richard Henderson | 1 | -3/+3 |
2022-03-03 | target/riscv: hardwire mstatus.FS to zero when enable zfinx | Weiwei Li | 1 | -1/+5 |
2022-02-16 | target/riscv: add support for svpbmt extension | Weiwei Li | 1 | -1/+3 |
2022-02-16 | target/riscv: add support for svnapot extension | Weiwei Li | 1 | -3/+15 |
2022-02-16 | target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE | Weiwei Li | 1 | -0/+3 |
2022-02-16 | target/riscv: Ignore reserved bits in PTE for RV64 | Guo Ren | 1 | -1/+12 |
2022-02-16 | target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 | Anup Patel | 1 | -5/+5 |
2022-02-16 | target/riscv: Implement AIA local interrupt priorities | Anup Patel | 1 | -21/+260 |
2022-02-16 | target/riscv: Allow AIA device emulation to set ireg rmw callback | Anup Patel | 1 | -0/+14 |
2022-02-16 | target/riscv: Improve delivery of guest external interrupts | Anup Patel | 1 | -0/+13 |
2022-02-16 | target/riscv: Implement hgeie and hgeip CSRs | Anup Patel | 1 | -3/+34 |
2022-01-21 | target/riscv: Split out the vill from vtype | LIU Zhiwei | 1 | -2/+1 |
2022-01-21 | target/riscv: Split pm_enabled into mask and base | LIU Zhiwei | 1 | -18/+6 |
2022-01-21 | target/riscv: Create current pm fields in env | LIU Zhiwei | 1 | -0/+43 |
2022-01-21 | target/riscv: Ignore the pc bits above XLEN | LIU Zhiwei | 1 | -1/+1 |
2022-01-21 | target/riscv: Create xl field in env | LIU Zhiwei | 1 | -32/+2 |
2022-01-21 | target/riscv: rvv-1.0: Add Zve32f extension into RISC-V | Frank Chang | 1 | -1/+1 |
2022-01-21 | target/riscv: rvv-1.0: Add Zve64f extension into RISC-V | Frank Chang | 1 | -1/+4 |
2022-01-08 | target/riscv: Implement the stval/mtval illegal instruction | Alistair Francis | 1 | -0/+3 |
2022-01-08 | target/riscv: Fixup setting GVA | Alistair Francis | 1 | -15/+6 |
2021-12-20 | target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation | Frank Chang | 1 | -3/+13 |
2021-12-20 | target/riscv: rvv-1.0: add translation-time vector context status | Frank Chang | 1 | -0/+3 |
2021-12-20 | target/riscv: rvv-1.0: add mstatus VS field | LIU Zhiwei | 1 | -1/+19 |
2021-11-02 | target/riscv: Make riscv_cpu_tlb_fill sysemu only | Richard Henderson | 1 | -20/+1 |
2021-10-29 | target/riscv: remove force HS exception | Jose Martins | 1 | -25/+1 |
2021-10-29 | target/riscv: fix VS interrupts forwarding to HS | Jose Martins | 1 | -20/+8 |
2021-10-28 | target/riscv: Implement address masking functions required for RISC-V Pointer... | Anatoly Parshintsev | 1 | -0/+18 |