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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-22target/riscv/cpu_helper.c: Fix mxr bit behaviorIvan Klokov1-4/+20
2023-11-22target/riscv/cpu_helper.c: Invalid exception on MMU translation stageIvan Klokov1-23/+7
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-11/+37
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-7/+19
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal1-7/+18
2023-11-07target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal1-6/+4
2023-10-12target/riscv: Use env_archcpu for better performanceRichard W.M. Jones1-2/+1
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li1-3/+3
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien1-1/+0
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li1-2/+5
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li1-0/+1
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li1-1/+2
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-13target/riscv: Fix initialized value for cur_pmmaskWeiwei Li1-2/+2
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale1-0/+6
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li1-4/+4
2023-06-13target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmpWeiwei Li1-10/+6
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li1-5/+2
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson1-0/+1
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti1-4/+11
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova1-9/+16
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson1-11/+11
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson1-33/+36
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson1-6/+6
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson1-1/+1
2023-05-05target/riscv: Suppress pte update with is_debugRichard Henderson1-1/+1
2023-05-05target/riscv: Move leaf pte processing out of level loopRichard Henderson1-111/+123
2023-05-05target/riscv: Hoist pbmte and hade out of the level loopRichard Henderson1-8/+8
2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson1-10/+2
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson1-4/+8
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson1-32/+17
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson1-9/+1
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson1-14/+6
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson1-5/+1
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson1-1/+1
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson1-1/+1
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-17/+9
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu1-2/+15
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu1-1/+3
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-0/+1
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson1-17/+16
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei1-5/+6
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei1-0/+1
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li1-6/+2
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li1-1/+1
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-1/+2
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-19/+38
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-81/+82
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-28/+23
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li1-2/+2
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