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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-1/+5
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-1/+3
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-3/+15
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li1-0/+3
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-1/+12
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-5/+5
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-21/+260
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel1-0/+14
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel1-0/+13
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-3/+34
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-2/+1
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-18/+6
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+43
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-32/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-1/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-1/+4
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+3
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang1-3/+13
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang1-0/+3
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-1/+19
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson1-20/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-25/+1
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins1-20/+8
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-0/+18
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-2/+1
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+33
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-6/+6
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson1-0/+46
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-5/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-8/+24
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis1-9/+15
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink1-8/+12
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis1-2/+2
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-6/+6
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer1-13/+8
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer1-1/+1
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer1-11/+14
2021-03-22target/riscv: add log of PMP permission checkingJim Shu1-0/+12
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu1-21/+63
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+10
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis1-5/+7
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang1-1/+2
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-36/+24
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis1-1/+1
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