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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)AuthorFilesLines
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-6/+3
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra1-0/+25
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-3/+8
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-1/+2
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel1-6/+246
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel1-69/+65
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson1-1/+1
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker1-1/+1
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel1-0/+1
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel1-2/+1
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang1-2/+2
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson1-3/+3
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li1-1/+5
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-1/+3
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-3/+15
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li1-0/+3
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-1/+12
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel1-5/+5
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel1-21/+260
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel1-0/+14
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel1-0/+13
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-3/+34
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei1-2/+1
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei1-18/+6
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei1-0/+43
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-32/+2
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-1/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-1/+4
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+3
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang1-3/+13
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang1-0/+3
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-1/+19
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson1-20/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-25/+1
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins1-20/+8
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-0/+18
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson1-2/+1
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+33
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-6/+6
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson1-0/+46
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang1-1/+2
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-5/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-8/+24
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis1-9/+15
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink1-8/+12
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