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path: root/target/riscv/cpu_bits.h
AgeCommit message (Expand)AuthorFilesLines
2023-03-01target/riscv: Add csr support for svaduWeiwei Li1-0/+4
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale1-0/+37
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang1-0/+1
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak1-2/+0
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+55
2022-09-07target/riscv: Add vstimecmp supportAtish Patra1-0/+4
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+4
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel1-1/+1
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel1-21/+3
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra1-0/+4
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li1-0/+9
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra1-0/+39
2022-04-22target/riscv: Add support for mconfigptrAtish Patra1-0/+1
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li1-0/+2
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li1-0/+1
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren1-0/+3
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel1-0/+119
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel1-0/+1
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel1-0/+3
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei1-0/+3
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot1-0/+3
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu1-0/+1
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei1-0/+7
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei1-0/+1
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-0/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-6/+0
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo1-0/+96
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson1-3/+5
2021-10-22target/riscv: Remove some unused macrosAlistair Francis1-8/+0
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng1-4/+4
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis1-2/+2
2021-06-08target/riscv: fix wfi exception behaviorJose Martins1-0/+1
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-11/+0
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-10/+0
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis1-11/+0
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis1-6/+0
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying1-0/+3
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis1-21/+23
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-23/+0
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang1-0/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+1
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis1-3/+1
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson1-2/+2
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-1/+0
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-15/+4
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-0/+6
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis1-0/+3
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis1-6/+8
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-0/+1
generated by cgit v1.1 at 2024-12-29 14:01:23 +0000