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path: root/target/riscv/cpu_bits.h
AgeCommit message (Expand)AuthorFilesLines
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot1-0/+3
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu1-0/+1
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei1-0/+7
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei1-0/+1
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-0/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-6/+0
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo1-0/+96
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson1-3/+5
2021-10-22target/riscv: Remove some unused macrosAlistair Francis1-8/+0
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng1-4/+4
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis1-2/+2
2021-06-08target/riscv: fix wfi exception behaviorJose Martins1-0/+1
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis1-11/+0
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-10/+0
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis1-11/+0
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis1-6/+0
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying1-0/+3
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis1-21/+23
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-23/+0
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang1-0/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+1
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis1-3/+1
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson1-2/+2
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis1-1/+0
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang1-15/+4
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-0/+6
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis1-0/+3
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis1-6/+8
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-0/+1
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis1-2/+3
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+1
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis1-0/+1
2020-07-02target/riscv: support vector extension csrLIU Zhiwei1-0/+15
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-0/+11
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis1-0/+3
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis1-0/+7
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis1-0/+6
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis1-0/+3
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis1-6/+6
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis1-16/+19
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis1-13/+21
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis1-17/+18
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis1-0/+1
2019-06-12Supply missing header guardsMarkus Armbruster1-0/+5
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis1-0/+11
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis1-0/+18
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis1-3/+6
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis1-3/+2
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis1-1/+1
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