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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza1-1/+6
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li1-7/+42
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé1-0/+2
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li1-113/+1
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza1-0/+1
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza1-0/+2
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza1-45/+1
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson1-1/+0
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-4/+2
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu1-2/+0
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu1-1/+1
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-0/+1
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson1-9/+7
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei1-8/+7
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei1-0/+8
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei1-0/+2
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li1-1/+1
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza1-4/+1
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza1-1/+1
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza1-1/+0
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li1-2/+2
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-12/+14
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-1/+0
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei1-1/+1
2023-05-05target/riscv: Add support for ZceWeiwei Li1-0/+1
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li1-0/+4
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li1-0/+6
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li1-1/+2
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti1-2/+6
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti1-0/+21
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner1-0/+2
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+2
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt1-0/+1
2023-03-01target/riscv: Add csr support for svaduWeiwei Li1-0/+1
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+1
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt1-0/+3
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li1-0/+3
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza1-12/+0
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