index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-07-10
target/riscv/cpu: add misa_ext_info_arr[]
Daniel Henrique Barboza
1
-1
/
+6
2023-07-10
target/riscv: Add additional xlen for address when MPRV=1
Weiwei Li
1
-7
/
+42
2023-06-28
target/riscv: Restrict KVM-specific fields from ArchCPU
Philippe Mathieu-Daudé
1
-0
/
+2
2023-06-26
target: Widen pc/cs_base in cpu_get_tb_cpu_state
Anton Johansson
1
-2
/
+2
2023-06-13
target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
Weiwei Li
1
-113
/
+1
2023-06-13
target/riscv: rework write_misa()
Daniel Henrique Barboza
1
-0
/
+1
2023-06-13
target/riscv: add PRIV_VERSION_LATEST
Daniel Henrique Barboza
1
-0
/
+2
2023-05-05
target/riscv: add CPU QOM header
Daniel Henrique Barboza
1
-45
/
+1
2023-05-05
target/riscv: Introduce mmuidx_2stage
Richard Henderson
1
-1
/
+0
2023-05-05
target/riscv: Handle HLV, HSV via helpers
Richard Henderson
1
-4
/
+2
2023-05-05
target/riscv: Reduce overhead of MSTATUS_SUM change
Fei Wu
1
-2
/
+0
2023-05-05
target/riscv: Separate priv from mmu_idx
Fei Wu
1
-1
/
+1
2023-05-05
target/riscv: Add a tb flags field for vstart
LIU Zhiwei
1
-0
/
+1
2023-05-05
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
Richard Henderson
1
-9
/
+7
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
1
-8
/
+7
2023-05-05
target/riscv: Add a general status enum for extensions
LIU Zhiwei
1
-0
/
+8
2023-05-05
target/riscv: Extract virt enabled state from tb flags
LIU Zhiwei
1
-0
/
+2
2023-05-05
target/riscv: Use PRV_RESERVED instead of PRV_H
Weiwei Li
1
-1
/
+1
2023-05-05
target/riscv/cpu.c: redesign register_cpu_props()
Daniel Henrique Barboza
1
-4
/
+1
2023-05-05
target/riscv: add RVG and remove cpu->cfg.ext_g
Daniel Henrique Barboza
1
-1
/
+1
2023-05-05
target/riscv: remove cpu->cfg.ext_v
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_j
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_h
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_u
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_s
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_m
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_e
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_i
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_f
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_d
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_c
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_a
Daniel Henrique Barboza
1
-1
/
+0
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
1
-2
/
+2
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
1
-12
/
+14
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
1
-1
/
+0
2023-05-05
target/riscv: Convert env->virt to a bool env->virt_enabled
LIU Zhiwei
1
-1
/
+1
2023-05-05
target/riscv: Add support for Zce
Weiwei Li
1
-0
/
+1
2023-05-05
target/riscv: add support for Zcmt extension
Weiwei Li
1
-0
/
+4
2023-05-05
target/riscv: add cfg properties for Zc* extension
Weiwei Li
1
-0
/
+6
2023-05-05
target/riscv: Simplify type conversion for CPURISCVState
Weiwei Li
1
-1
/
+2
2023-03-06
riscv: Introduce satp mode hw capabilities
Alexandre Ghiti
1
-2
/
+6
2023-03-06
riscv: Allow user to set the satp mode
Alexandre Ghiti
1
-0
/
+21
2023-03-05
target/riscv: implement Zicbom extension
Christoph Muellner
1
-0
/
+2
2023-03-05
target/riscv: implement Zicboz extension
Christoph Muellner
1
-0
/
+2
2023-03-01
Merge patch series "target/riscv: Add support for Svadu extension"
Palmer Dabbelt
1
-0
/
+1
2023-03-01
target/riscv: Add csr support for svadu
Weiwei Li
1
-0
/
+1
2023-03-01
target/riscv: Add support for Zicond extension
Weiwei Li
1
-0
/
+1
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
1
-0
/
+3
2023-03-01
target/riscv: Add cfg properties for Zv* extensions
Weiwei Li
1
-0
/
+3
2023-03-01
target/riscv/cpu: remove CPUArchState::features and friends
Daniel Henrique Barboza
1
-12
/
+0
[next]