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cpu.h
Age
Commit message (
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Author
Files
Lines
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
1
-0
/
+31
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
1
-0
/
+7
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
1
-0
/
+1
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
1
-0
/
+3
2022-01-08
target/riscv: Implement the stval/mtval illegal instruction
Alistair Francis
1
-0
/
+2
2022-01-08
target/riscv: actual functions to realize crs 128-bit insns
Frédéric Pétrot
1
-0
/
+7
2022-01-08
target/riscv: helper functions to wrap calls to 128-bit csr insns
Frédéric Pétrot
1
-0
/
+5
2022-01-08
target/riscv: adding high part of some csrs
Frédéric Pétrot
1
-0
/
+4
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
1
-0
/
+3
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
1
-0
/
+1
2022-01-08
target/riscv: array for the 64 upper bits of 128-bit registers
Frédéric Pétrot
1
-0
/
+2
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
1
-0
/
+1
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
Frank Chang
1
-9
/
+18
2021-12-20
target/riscv: rvv-1.0: add VMA and VTA
Frank Chang
1
-0
/
+2
2021-12-20
target/riscv: rvv-1.0: add fractional LMUL
Frank Chang
1
-12
/
+14
2021-12-20
target/riscv: rvv-1.0: add translation-time vector context status
Frank Chang
1
-2
/
+3
2021-12-20
target/riscv: rvv-1.0: add mstatus VS field
LIU Zhiwei
1
-0
/
+2
2021-12-20
target/riscv: drop vector 0.7.1 and add 1.0 support
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: zfh: implement zfhmin extension
Frank Chang
1
-0
/
+1
2021-12-20
target/riscv: zfh: half-precision load and store
Kito Cheng
1
-0
/
+1
2021-10-29
target/riscv: remove force HS exception
Jose Martins
1
-2
/
+0
2021-10-28
target/riscv: Implement address masking functions required for RISC-V Pointer...
Anatoly Parshintsev
1
-0
/
+2
2021-10-28
target/riscv: Support CSRs required for RISC-V PM extension except for the h-...
Alexey Baturo
1
-0
/
+11
2021-10-28
target/riscv: Add J-extension into RISC-V
Alexey Baturo
1
-0
/
+2
2021-10-22
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
Richard Henderson
1
-0
/
+2
2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
1
-1
/
+8
2021-10-22
target/riscv: Split misa.mxl and misa.ext
Richard Henderson
1
-7
/
+8
2021-10-22
target/riscv: Move cpu_get_tb_cpu_state out of line
Richard Henderson
1
-45
/
+2
2021-10-22
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Frank Chang
1
-7
/
+7
2021-10-07
target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
Frank Chang
1
-0
/
+4
2021-10-07
target/riscv: Remove RVB (replaced by Zb[abcs])
Philipp Tomsich
1
-3
/
+0
2021-10-07
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Philipp Tomsich
1
-0
/
+4
2021-09-21
hw/core: Make do_unaligned_access noreturn
Richard Henderson
1
-1
/
+1
2021-09-21
include/exec: Move cpu_signal_handler declaration
Richard Henderson
1
-2
/
+0
2021-09-14
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Philippe Mathieu-Daudé
1
-1
/
+1
2021-06-08
target/riscv: rvb: add b-ext version cpu option
Frank Chang
1
-0
/
+3
2021-06-08
target/riscv: rvb: support and turn on B-extension from command line
Kito Cheng
1
-0
/
+1
2021-06-08
target/riscv: rvb: count leading/trailing zeros
Kito Cheng
1
-0
/
+1
2021-06-08
target/riscv: Remove unnecessary riscv_*_names[] declaration
Bin Meng
1
-2
/
+0
2021-06-08
target/riscv: Do not include 'pmp.h' in user emulation
Philippe Mathieu-Daudé
1
-0
/
+2
2021-05-11
target/riscv: Remove the hardcoded RVXLEN macro
Alistair Francis
1
-6
/
+0
2021-05-11
target/riscv: Add a config option for ePMP
Hou Weiying
1
-0
/
+1
2021-05-11
target/riscv: Add ePMP CSR access functions
Hou Weiying
1
-0
/
+1
2021-05-11
target/riscv: Add the ePMP feature
Alistair Francis
1
-0
/
+1
2021-05-11
target/riscv: Use RISCVException enum for CSR access
Alistair Francis
1
-4
/
+7
2021-05-11
target/riscv: Use the RISCVException enum for CSR operations
Alistair Francis
1
-6
/
+8
2021-05-11
target/riscv: Use the RISCVException enum for CSR predicates
Alistair Francis
1
-1
/
+2
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