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path: root/target/riscv/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2022-01-21target/riscv: Create xl field in envLIU Zhiwei1-0/+31
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang1-0/+1
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang1-0/+1
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang1-0/+7
2022-01-21target/riscv: Add host cpu typeYifei Jiang1-0/+1
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-0/+3
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis1-0/+2
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot1-0/+7
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot1-0/+5
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot1-0/+4
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot1-0/+3
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot1-0/+1
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot1-0/+2
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang1-0/+1
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang1-9/+18
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang1-0/+2
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang1-12/+14
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang1-2/+3
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei1-0/+2
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang1-1/+1
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang1-0/+1
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng1-0/+1
2021-10-29target/riscv: remove force HS exceptionJose Martins1-2/+0
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev1-0/+2
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo1-0/+11
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo1-0/+2
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson1-0/+2
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-1/+8
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson1-7/+8
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson1-45/+2
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang1-7/+7
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang1-0/+4
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich1-3/+0
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich1-0/+4
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-1/+1
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-1/+1
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang1-0/+3
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng1-0/+1
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+1
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng1-2/+0
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé1-0/+2
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis1-6/+0
2021-05-11target/riscv: Add a config option for ePMPHou Weiying1-0/+1
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying1-0/+1
2021-05-11target/riscv: Add the ePMP featureAlistair Francis1-0/+1
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis1-4/+7
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis1-6/+8
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis1-1/+2
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