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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé1-2/+1
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford1-1/+39
2023-11-07target/riscv: cpu: Set the OpenTitan priv to 1.12.0Alistair Francis1-1/+1
2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou1-18/+18
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou1-0/+2
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou1-0/+2
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza1-0/+3
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza1-0/+12
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale1-0/+11
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan1-5/+3
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza1-0/+9
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza1-2/+16
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-1/+2
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal1-1/+2
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza1-3/+3
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza1-3/+3
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza1-11/+11
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza1-11/+11
2023-10-12target/riscv: deprecate capital 'Z' CPU propertiesDaniel Henrique Barboza1-11/+28
2023-10-12target/riscv: add riscv_cpu_get_name()Daniel Henrique Barboza1-0/+11
2023-10-12target/riscv/cpu: move priv spec functions to tcg-cpu.cDaniel Henrique Barboza1-38/+0
2023-10-12target/riscv/cpu.c: export isa_edata_arr[]Daniel Henrique Barboza1-26/+21
2023-10-12target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.cDaniel Henrique Barboza1-90/+0
2023-10-12target/riscv/cpu.c: make misa_ext_cfgs[] 'const'Daniel Henrique Barboza1-13/+8
2023-10-12target/riscv/tcg: introduce tcg_cpu_instance_init()Daniel Henrique Barboza1-150/+0
2023-10-12target/riscv/cpu.c: export set_misa()Daniel Henrique Barboza1-16/+18
2023-10-12target/riscv/kvm: do not use riscv_cpu_add_misa_properties()Daniel Henrique Barboza1-0/+2
2023-10-12target/riscv: move KVM only files to kvm subdirDaniel Henrique Barboza1-1/+1
2023-10-12target/riscv: introduce KVM AccelCPUClassDaniel Henrique Barboza1-5/+3
2023-10-12target/riscv: make riscv_add_satp_mode_properties() publicDaniel Henrique Barboza1-3/+2
2023-10-12target/riscv: move riscv_cpu_add_kvm_properties() to kvm.cDaniel Henrique Barboza1-80/+5
2023-10-12target/riscv/cpu.c: mark extensions arrays as 'const'Daniel Henrique Barboza1-9/+13
2023-10-12target/riscv: move 'host' CPU declaration to kvm.cDaniel Henrique Barboza1-15/+0
2023-10-12target/riscv/cpu.c: add .instance_post_init()Daniel Henrique Barboza1-11/+32
2023-10-12target/riscv: move riscv_tcg_ops to tcg-cpu.cDaniel Henrique Barboza1-58/+0
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza1-356/+5
2023-10-12target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()Daniel Henrique Barboza1-128/+0
2023-10-12target/riscv: introduce TCG AccelCPUClassDaniel Henrique Barboza1-4/+1
2023-10-12target/riscv/cpu.c: consider user option with RVGDaniel Henrique Barboza1-2/+16
2023-10-12target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()Daniel Henrique Barboza1-0/+16
2023-10-12target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()Daniel Henrique Barboza1-9/+9
2023-10-12target/riscv/cpu.c: introduce RISCVCPUMultiExtConfigDaniel Henrique Barboza1-99/+159
2023-10-12target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()Daniel Henrique Barboza1-25/+25
2023-10-12target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()Daniel Henrique Barboza1-3/+40
2023-10-12target/riscv: make CPUCFG() macro publicDaniel Henrique Barboza1-1/+1
2023-10-12target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabledDaniel Henrique Barboza1-9/+9
2023-10-12target/riscv: deprecate the 'any' CPU typeDaniel Henrique Barboza1-0/+5
2023-10-12target/riscv: add 'max' CPU typeDaniel Henrique Barboza1-0/+56
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