| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-08-12 | target/ppc: Fix SPE unavailable exception triggering | Matthieu Bucchianeri | 1 | -33/+64 |
| 2020-08-12 | target/ppc: add vmulh{su}d instructions | Lijun Pan | 2 | -0/+4 |
| 2020-08-12 | target/ppc: add vmulh{su}w instructions | Lijun Pan | 2 | -2/+8 |
| 2020-08-12 | target/ppc: add vmulld instruction | Lijun Pan | 2 | -0/+5 |
| 2020-08-12 | target/ppc: convert vmuluwm to tcg_gen_gvec_mul | Lijun Pan | 1 | -1/+1 |
| 2020-08-12 | target/ppc: Fix TCG leak with the evmwsmiaa instruction | Matthieu Bucchianeri | 1 | -2/+2 |
| 2020-06-02 | target/ppc: Use tcg_gen_gvec_rotlv | Richard Henderson | 1 | -4/+4 |
| 2020-05-06 | target/ppc: Use tcg_gen_gvec_dup_imm | Richard Henderson | 2 | -15/+19 |
| 2020-02-21 | target/ppc: Fix typo in comments | BALATON Zoltan | 1 | -3/+3 |
| 2019-10-24 | target/ppc: Fix for optimized vsl/vsr instructions | Stefan Brankovic | 1 | -44/+40 |
| 2019-10-04 | ppc: Add support for 'mffsce' instruction | Paul A. Clarke | 2 | -0/+32 |
| 2019-10-04 | ppc: Add support for 'mffscrn','mffscrni' instructions | Paul A. Clarke | 2 | -1/+72 |
| 2019-08-29 | target/ppc: Refactor emulation of vmrgew and vmrgow instructions | Stefan Brankovic | 1 | -29/+37 |
| 2019-08-29 | ppc: Fix xsmaddmdp and friends | Paul A. Clarke | 1 | -1/+1 |
| 2019-08-21 | ppc: Add support for 'mffsl' instruction | Paul A. Clarke | 2 | -1/+25 |
| 2019-08-21 | target/ppc: Optimize emulation of vclzw instruction | Stefan Brankovic | 1 | -1/+27 |
| 2019-08-21 | target/ppc: Optimize emulation of vclzd instruction | Stefan Brankovic | 1 | -1/+27 |
| 2019-08-21 | target/ppc: Optimize emulation of vgbbd instruction | Stefan Brankovic | 1 | -1/+76 |
| 2019-08-21 | target/ppc: Optimize emulation of vsl and vsr instructions | Stefan Brankovic | 1 | -2/+99 |
| 2019-08-21 | target/ppc: Optimize emulation of lvsl and lvsr instructions | Stefan Brankovic | 1 | -32/+89 |
| 2019-07-02 | target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro | Mark Cave-Ayland | 2 | -66/+85 |
| 2019-07-02 | target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time | Mark Cave-Ayland | 1 | -5/+5 |
| 2019-07-02 | target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at transla... | Mark Cave-Ayland | 1 | -23/+24 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c | Mark Cave-Ayland | 1 | -3/+21 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -10/+28 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -8/+28 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -4/+20 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c | Mark Cave-Ayland | 1 | -6/+24 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -60/+75 |
| 2019-07-02 | target/ppc: introduce separate generator and helper for xscvqpdp | Mark Cave-Ayland | 1 | -1/+17 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -60/+77 |
| 2019-07-02 | target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions | Mark Cave-Ayland | 1 | -8/+41 |
| 2019-06-12 | target/ppc: Use tcg_gen_gvec_bitsel | Richard Henderson | 1 | -22/+2 |
| 2019-06-12 | target/ppc: Fix lxvw4x, lxvh8x and lxvb16x | Anton Blanchard | 1 | -6/+7 |
| 2019-05-29 | target/ppc: Use vector variable shifts for VSL, VSR, VSRA | Richard Henderson | 1 | -12/+12 |
| 2019-05-29 | target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p | Anton Blanchard | 1 | -2/+2 |
| 2019-05-29 | target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE | Anton Blanchard | 1 | -10/+58 |
| 2019-05-29 | target/ppc: Fix xxspltib | Anton Blanchard | 1 | -4/+4 |
| 2019-05-29 | target/ppc: Fix xxbrq, xxbrw | Anton Blanchard | 1 | -2/+2 |
| 2019-05-29 | target/ppc: Fix xvxsigdp | Anton Blanchard | 1 | -1/+1 |
| 2019-05-13 | target/ppc: Use tcg_gen_abs_i32 | Philippe Mathieu-Daudé | 1 | -13/+1 |
| 2019-05-13 | tcg: Specify optional vector requirements with a list | Richard Henderson | 1 | -1/+6 |
| 2019-04-26 | target/ppc: Style fixes for translate/spe-impl.inc.c | David Gibson | 1 | -5/+9 |
| 2019-04-26 | target/ppc: Style fixes for translate/vmx-impl.inc.c | David Gibson | 1 | -11/+15 |
| 2019-04-26 | target/ppc: Style fixes for translate/vsx-impl.inc.c | David Gibson | 1 | -7/+8 |
| 2019-04-26 | target/ppc: Style fixes for translate/fp-impl.inc.c | David Gibson | 1 | -20/+32 |
| 2019-03-29 | target/ppc: Fix QEMU crash with stxsdx | Greg Kurz | 1 | -1/+1 |
| 2019-03-12 | target/ppc: Optimize x[sv]xsigdp using deposit_i64() | Philippe Mathieu-Daudé | 1 | -8/+4 |
| 2019-03-12 | target/ppc: Optimize xviexpdp() using deposit_i64() | Philippe Mathieu-Daudé | 1 | -11/+3 |
| 2019-03-12 | target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and set_c... | Mark Cave-Ayland | 1 | -30/+4 |
