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2017-02-02
target-ppc: Add xststdc[sp, dp, qp] instructions
Nikunj A Dadhania
2
-0
/
+7
2017-02-02
target-ppc: Add xvtstdc[sp,dp] instructions
Nikunj A Dadhania
2
-0
/
+10
2017-01-31
target-ppc: Add xvcv[hpsp, sphp] instructions
Nikunj A Dadhania
2
-0
/
+4
2017-01-31
target-ppc: Add xsmulqp instruction
Bharata B Rao
2
-0
/
+2
2017-01-31
target-ppc: Add xsdivqp instruction
Bharata B Rao
2
-0
/
+2
2017-01-31
target-ppc: Add xscvsdqp and xscvudqp instructions
Bharata B Rao
2
-0
/
+4
2017-01-31
ppc: Implement bcdutrunc. instruction
Jose Ricardo Ziviani
2
-1
/
+5
2017-01-31
ppc: Implement bcdtrunc. instruction
Jose Ricardo Ziviani
2
-2
/
+7
2017-01-31
target-ppc: Add xscvqps[d,w]z instructions
Bharata B Rao
2
-0
/
+4
2017-01-31
target-ppc: Add xvxsigdp instruction
Nikunj A Dadhania
2
-0
/
+41
2017-01-31
target-ppc: Add xvxsigsp instruction
Nikunj A Dadhania
2
-0
/
+3
2017-01-31
target-ppc: Add xvxexpdp instruction
Nikunj A Dadhania
2
-0
/
+18
2017-01-31
target-ppc: Add xvxexpsp instruction
Nikunj A Dadhania
2
-0
/
+18
2017-01-31
target-ppc: Add xviexpdp instruction
Nikunj A Dadhania
2
-0
/
+27
2017-01-31
target-ppc: Add xviexpsp instruction
Nikunj A Dadhania
2
-0
/
+28
2017-01-31
target-ppc: Add xsiexpqp instruction
Nikunj A Dadhania
2
-0
/
+23
2017-01-31
target-ppc: Add xsiexpdp instruction
Nikunj A Dadhania
2
-0
/
+21
2017-01-31
ppc: Implement bcdsr. instruction
Jose Ricardo Ziviani
2
-0
/
+3
2017-01-31
ppc: Implement bcdus. instruction
Jose Ricardo Ziviani
2
-1
/
+4
2017-01-31
ppc: Implement bcds. instruction
Jose Ricardo Ziviani
2
-1
/
+5
2017-01-31
target-ppc: Add xscvqpdp instruction
Bharata B Rao
2
-0
/
+2
2017-01-31
target-ppc: Add xscvdpqp instruction
Bharata B Rao
2
-0
/
+2
2017-01-31
target-ppc: Add xsaddqp instructions
Bharata B Rao
2
-0
/
+2
2017-01-31
target-ppc: Add xsxsigqp instructions
Nikunj A Dadhania
2
-0
/
+30
2017-01-31
target-ppc: Add xsxsigdp instruction
Nikunj A Dadhania
2
-0
/
+30
2017-01-31
target-ppc: Add xsxexpqp instruction
Nikunj A Dadhania
2
-0
/
+16
2017-01-31
target-ppc: Add xsxexpdp instruction
Nikunj A Dadhania
2
-0
/
+17
2017-01-31
target-ppc: Add xscvdphp, xscvhpdp
Bharata B Rao
2
-0
/
+4
2017-01-31
target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
Bharata B Rao
1
-10
/
+10
2017-01-31
target-ppc: Add xxinsertw instruction
Nikunj A Dadhania
2
-2
/
+4
2017-01-31
target-ppc: Add xxextractuw instruction
Nikunj A Dadhania
2
-0
/
+35
2017-01-31
target-ppc: implement stxvll instructions
Nikunj A Dadhania
2
-0
/
+2
2017-01-31
target-ppc: implement stxvl instruction
Nikunj A Dadhania
2
-0
/
+4
2017-01-31
target-ppc: implement lxvll instruction
Nikunj A Dadhania
2
-0
/
+2
2017-01-31
target-ppc: implement lxvl instruction
Nikunj A Dadhania
2
-0
/
+32
2017-01-31
target-ppc: Add xxperm and xxpermr instructions
Bharata B Rao
2
-0
/
+4
2017-01-31
target-ppc: implement xscpsgnqp instruction
Nikunj A Dadhania
2
-1
/
+12
2017-01-31
target-ppc: implement xsnegqp instruction
Nikunj A Dadhania
2
-0
/
+5
2017-01-31
target-ppc: implement xsabsqp/xsnabsqp instruction
David Gibson
2
-0
/
+40
2017-01-31
target-ppc: add vextu[bhw][lr]x instructions
Avinesh Kumar
2
-2
/
+29
2017-01-31
target-ppc: Implement bcdsetsgn. instruction
Jose Ricardo Ziviani
1
-0
/
+8
2017-01-31
target-ppc: Implement bcdcpsgn. instruction
Jose Ricardo Ziviani
2
-1
/
+4
2017-01-31
target-ppc: Implement bcdctsq. instruction
Jose Ricardo Ziviani
1
-0
/
+7
2017-01-31
target-ppc: Implement bcdcfsq. instruction
Jose Ricardo Ziviani
1
-0
/
+7
2017-01-31
target-ppc: implement lxv/lxvx and stxv/stxvx
Nikunj A Dadhania
2
-0
/
+52
2017-01-31
target-ppc: implement stxsd and stxssp
Nikunj A Dadhania
2
-1
/
+21
2017-01-31
target-ppc: implement lxsd and lxssp instructions
Nikunj A Dadhania
2
-1
/
+21
2017-01-31
target-ppc: Add xscmpoqp and xscmpuqp instructions
Bharata B Rao
2
-0
/
+4
2017-01-31
target-ppc: Add xscmpexp[dp,qp] instructions
Bharata B Rao
2
-0
/
+8
2016-12-20
Move target-* CPU file into a target/ folder
Thomas Huth
10
-0
/
+5628