| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-08-21 | target/ppc: Optimize emulation of vclzw instruction | Stefan Brankovic | 1 | -3/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vclzd instruction | Stefan Brankovic | 1 | -3/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vgbbd instruction | Stefan Brankovic | 1 | -276/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vsl and vsr instructions | Stefan Brankovic | 1 | -35/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of lvsl and lvsr instructions | Stefan Brankovic | 1 | -18/+0 |
| 2019-08-16 | Include qemu/main-loop.h less | Markus Armbruster | 1 | -0/+2 |
| 2019-07-02 | target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time | Mark Cave-Ayland | 1 | -8/+4 |
| 2019-07-02 | target/ppc: remove getVSR()/putVSR() from int_helper.c | Mark Cave-Ayland | 1 | -12/+10 |
| 2019-05-29 | target/ppc: Use vector variable shifts for VSL, VSR, VSRA | Richard Henderson | 1 | -37/+0 |
| 2019-05-29 | target/ppc: Fix vsum2sws | Anton Blanchard | 1 | -1/+1 |
| 2019-05-29 | target/ppc: Fix vslv and vsrv | Anton Blanchard | 1 | -7/+7 |
| 2019-05-22 | target/ppc: Use qemu_guest_getrandom for DARN | Richard Henderson | 1 | -11/+26 |
| 2019-04-26 | target/ppc: Style fixes for int_helper.c | David Gibson | 1 | -31/+39 |
| 2019-02-18 | target/ppc: convert vmin* and vmax* to vector operations | Richard Henderson | 1 | -27/+0 |
| 2019-02-18 | target/ppc: convert vadd*s and vsub*s to vector operations | Richard Henderson | 1 | -14/+4 |
| 2019-02-18 | target/ppc: Split out VSCR_SAT to a vector field | Richard Henderson | 1 | -3/+8 |
| 2019-02-18 | target/ppc: Add set_vscr_sat | Richard Henderson | 1 | -12/+17 |
| 2019-02-18 | target/ppc: Add helper_mfvscr | Richard Henderson | 1 | -0/+5 |
| 2019-02-18 | target/ppc: Pass integer to helper_mtvscr | Richard Henderson | 1 | -3/+3 |
| 2019-02-18 | target/ppc: convert vsplt[bhw] to use vector operations | Richard Henderson | 1 | -19/+0 |
| 2019-02-18 | target/ppc: convert vspltis[bhw] to use vector operations | Richard Henderson | 1 | -15/+0 |
| 2019-02-18 | target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper... | Mark Cave-Ayland | 1 | -7/+0 |
| 2019-02-04 | target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.c | Mark Cave-Ayland | 1 | -110/+45 |
| 2019-02-04 | target/ppc: remove ROTRu32 and ROTRu64 macros from int_helper.c | Mark Cave-Ayland | 1 | -28/+20 |
| 2019-02-04 | target/ppc: simplify VEXT_SIGNED macro in int_helper.c | Mark Cave-Ayland | 1 | -7/+7 |
| 2019-02-04 | target/ppc: eliminate use of EL_IDX macros from int_helper.c | Mark Cave-Ayland | 1 | -39/+27 |
| 2019-02-04 | target/ppc: eliminate use of HI_IDX and LO_IDX macros from int_helper.c | Mark Cave-Ayland | 1 | -95/+85 |
| 2019-02-04 | target/ppc: rework vmul{e,o}{s,u}{b,h,w} instructions to use Vsr* macros | Mark Cave-Ayland | 1 | -21/+27 |
| 2019-02-04 | target/ppc: rework vmrg{l,h}{b,h,w} instructions to use Vsr* macros | Mark Cave-Ayland | 1 | -35/+19 |
| 2019-01-09 | target/ppc: replace AVR* macros with Vsr* macros | Mark Cave-Ayland | 1 | -17/+13 |
| 2019-01-09 | target/ppc: merge ppc_vsr_t and ppc_avr_t union types | Mark Cave-Ayland | 1 | -27/+29 |
| 2018-08-21 | target/ppc: simplify bcdadd/sub functions | Yasmin Beatriz | 1 | -31/+18 |
| 2018-08-21 | target/ppc: bcdsub fix sign when result is zero | Yasmin Beatriz | 1 | -0/+3 |
| 2018-07-07 | target/ppc: fix build on ppc64 host | Laurent Vivier | 1 | -1/+1 |
| 2018-06-01 | target: Do not include "exec/exec-all.h" if it is not necessary | Philippe Mathieu-Daudé | 1 | -1/+0 |
| 2018-05-11 | rename included C files to foo.inc.c, remove osdep.h | Paolo Bonzini | 1 | -1/+1 |
| 2018-02-21 | target/*/cpu.h: remove softfloat.h | Alex Bennée | 1 | -0/+1 |
| 2018-01-10 | target/ppc: more use of the PPC_*() macros | Cédric Le Goater | 1 | -1/+1 |
| 2017-10-17 | target/ppc: Fix carry flag setting for shift algebraic instructions | Sandipan Das | 1 | -8/+8 |
| 2017-03-01 | target/ppc: introduce helper_update_ov_legacy | Nikunj A Dadhania | 1 | -21/+13 |
| 2017-01-31 | ppc: Implement bcdutrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+51 |
| 2017-01-31 | ppc: Implement bcdtrunc. instruction | Jose Ricardo Ziviani | 1 | -0/+37 |
| 2017-01-31 | ppc: Implement bcdsr. instruction | Jose Ricardo Ziviani | 1 | -0/+48 |
| 2017-01-31 | ppc: Implement bcdus. instruction | Jose Ricardo Ziviani | 1 | -0/+41 |
| 2017-01-31 | ppc: Implement bcds. instruction | Jose Ricardo Ziviani | 1 | -0/+40 |
| 2017-01-31 | ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro | Jose Ricardo Ziviani | 1 | -3/+3 |
| 2017-01-31 | target-ppc: Add xxinsertw instruction | Nikunj A Dadhania | 1 | -0/+25 |
| 2017-01-31 | target-ppc: Add xxextractuw instruction | Nikunj A Dadhania | 1 | -0/+26 |
| 2017-01-31 | target-ppc: Implement bcd_is_valid function | Jose Ricardo Ziviani | 1 | -7/+20 |
| 2017-01-31 | target-ppc: add vextu[bhw][lr]x instructions | Avinesh Kumar | 1 | -0/+36 |
