| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-02-09 | target/ppc: Remove PowerPC 601 CPUs | Cédric Le Goater | 1 | -13/+0 |
| 2022-01-28 | target/ppc: Remove support for the PowerPC 602 CPU | Cédric Le Goater | 1 | -1/+0 |
| 2022-01-28 | ppc/ppc405: Fix TLB flushing | Cédric Le Goater | 1 | -0/+1 |
| 2022-01-18 | target/ppc: Finish removal of 401/403 CPUs | Cédric Le Goater | 1 | -1/+0 |
| 2022-01-04 | ppc/ppc405: Restore TCR and STR write handlers | Cédric Le Goater | 1 | -0/+2 |
| 2021-12-17 | PPC64/TCG: Implement 'rfebb' instruction | Daniel Henrique Barboza | 1 | -0/+1 |
| 2021-12-17 | target/ppc: enable PMU instruction count | Daniel Henrique Barboza | 1 | -0/+1 |
| 2021-12-17 | target/ppc: PMU: update counters on MMCR1 write | Daniel Henrique Barboza | 1 | -0/+1 |
| 2021-12-17 | target/ppc: PMU: update counters on PMCs r/w | Daniel Henrique Barboza | 1 | -0/+2 |
| 2021-12-17 | target/ppc: PMU basic cycle count for pseries TCG | Daniel Henrique Barboza | 1 | -0/+1 |
| 2021-12-17 | target/ppc: move xscvqpdp to decodetree | Matheus Ferst | 1 | -1/+1 |
| 2021-12-17 | target/ppc: Fix xs{max, min}[cj]dp to use VSX registers | Victor Colombo | 1 | -4/+4 |
| 2021-12-17 | target/ppc: Remove the software TLB model of 7450 CPUs | Fabiano Rosas | 1 | -2/+0 |
| 2021-12-17 | target/ppc: Add helper for frsqrtes | Richard Henderson | 1 | -0/+1 |
| 2021-12-17 | target/ppc: Add helper for fmuls | Richard Henderson | 1 | -0/+1 |
| 2021-12-17 | target/ppc: Add helpers for fadds, fsubs, fdivs | Richard Henderson | 1 | -0/+3 |
| 2021-12-17 | target/ppc: Add helper for fsqrts | Richard Henderson | 1 | -0/+1 |
| 2021-12-17 | target/ppc: Add helpers for fmadds et al | Richard Henderson | 1 | -0/+4 |
| 2021-12-17 | target/ppc: Fixed call to deferred exception | Lucas Mateus Castro (alqotel) | 1 | -0/+1 |
| 2021-11-09 | target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions | Matheus Ferst | 1 | -0/+4 |
| 2021-11-09 | target/ppc: Implement Vector Extract Double to VSR using GPR index insns | Matheus Ferst | 1 | -0/+4 |
| 2021-11-09 | target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree | Matheus Ferst | 1 | -4/+0 |
| 2021-11-09 | target/ppc: Implement Vector Insert from GPR using GPR index insns | Matheus Ferst | 1 | -0/+4 |
| 2021-11-09 | target/ppc: Implement vpdepd/vpextd instruction | Matheus Ferst | 1 | -1/+1 |
| 2021-11-09 | target/ppc: Move vcfuged to vmx-impl.c.inc | Matheus Ferst | 1 | -1/+1 |
| 2021-11-09 | target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree | Luis Pires | 1 | -8/+8 |
| 2021-11-09 | target/ppc: Move dct{dp,qpq},dr{sp,dpq},dc{f,t}fix[q],dxex[q] to decodetree | Luis Pires | 1 | -10/+10 |
| 2021-11-09 | target/ppc: Move dqua[q], drrnd[q] to decodetree | Luis Pires | 1 | -4/+4 |
| 2021-11-09 | target/ppc: Move dquai[q], drint{x,n}[q] to decodetree | Luis Pires | 1 | -6/+6 |
| 2021-11-09 | target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree | Luis Pires | 1 | -10/+10 |
| 2021-11-09 | target/ppc: Move d{add,sub,mul,div,iex}[q] to decodetree | Luis Pires | 1 | -10/+10 |
| 2021-11-09 | target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree | Luis Pires | 1 | -4/+4 |
| 2021-11-09 | target/ppc: Implement DCTFIXQQ | Luis Pires | 1 | -0/+1 |
| 2021-11-09 | target/ppc: Implement DCFFIXQQ | Luis Pires | 1 | -0/+1 |
| 2021-11-09 | target/ppc: Implement pextd instruction | Matheus Ferst | 1 | -0/+1 |
| 2021-11-09 | target/ppc: Implement pdepd instruction | Matheus Ferst | 1 | -0/+1 |
| 2021-06-19 | tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode | Richard Henderson | 1 | -3/+0 |
| 2021-06-03 | target/ppc: Implement cfuged instruction | Matheus Ferst | 1 | -0/+1 |
| 2021-05-19 | target/ppc: Mark helper_raise_exception* as noreturn | Richard Henderson | 1 | -2/+2 |
| 2021-05-04 | target/ppc: Create helper_scv | Richard Henderson | 1 | -0/+1 |
| 2020-08-12 | target/ppc: add vmulh{su}d instructions | Lijun Pan | 1 | -0/+2 |
| 2020-08-12 | target/ppc: add vmulh{su}w instructions | Lijun Pan | 1 | -0/+2 |
| 2020-08-12 | target/ppc: convert vmuluwm to tcg_gen_gvec_mul | Lijun Pan | 1 | -1/+0 |
| 2020-06-02 | target/ppc: Use tcg_gen_gvec_rotlv | Richard Henderson | 1 | -4/+0 |
| 2020-05-27 | target/ppc: Add support for scv and rfscv instructions | Nicholas Piggin | 1 | -0/+1 |
| 2020-03-24 | target/ppc: Fix ISA v3.0 (POWER9) slbia implementation | Nicholas Piggin | 1 | -1/+1 |
| 2020-02-02 | target/ppc: Add privileged message send facilities | Cédric Le Goater | 1 | -0/+4 |
| 2019-12-17 | target/ppc: Add SPR TBU40 | Suraj Jitindar Singh | 1 | -0/+1 |
| 2019-12-17 | target/ppc: Work [S]PURR implementation and add HV support | Suraj Jitindar Singh | 1 | -0/+1 |
| 2019-12-17 | target/ppc: Implement the VTB for HV access | Suraj Jitindar Singh | 1 | -0/+2 |
