| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-10-04 | target/ppc: update {get,set}_dfp{64,128}() helper functions to read/write DFP... | Mark Cave-Ayland | 1 | -1/+1 |
| 2019-08-21 | target/ppc: Optimize emulation of vclzw instruction | Stefan Brankovic | 1 | -1/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vclzd instruction | Stefan Brankovic | 1 | -1/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vgbbd instruction | Stefan Brankovic | 1 | -1/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of vsl and vsr instructions | Stefan Brankovic | 1 | -2/+0 |
| 2019-08-21 | target/ppc: Optimize emulation of lvsl and lvsr instructions | Stefan Brankovic | 1 | -2/+0 |
| 2019-07-02 | target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro | Mark Cave-Ayland | 1 | -32/+16 |
| 2019-07-02 | target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time | Mark Cave-Ayland | 1 | -2/+2 |
| 2019-07-02 | target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at transla... | Mark Cave-Ayland | 1 | -4/+4 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c | Mark Cave-Ayland | 1 | -3/+3 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -10/+10 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -8/+8 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -4/+4 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c | Mark Cave-Ayland | 1 | -6/+6 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -60/+60 |
| 2019-07-02 | target/ppc: introduce separate generator and helper for xscvqpdp | Mark Cave-Ayland | 1 | -1/+1 |
| 2019-07-02 | target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c | Mark Cave-Ayland | 1 | -60/+60 |
| 2019-07-02 | target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions | Mark Cave-Ayland | 1 | -8/+12 |
| 2019-05-29 | target/ppc: Use vector variable shifts for VSL, VSR, VSRA | Richard Henderson | 1 | -12/+0 |
| 2019-02-26 | target/ppc: Flush the TLB locally when the LPIDR is written | Benjamin Herrenschmidt | 1 | -0/+1 |
| 2019-02-18 | target/ppc: convert vmin* and vmax* to vector operations | Richard Henderson | 1 | -16/+0 |
| 2019-02-18 | target/ppc: convert vadd*s and vsub*s to vector operations | Richard Henderson | 1 | -12/+12 |
| 2019-02-18 | target/ppc: Add helper_mfvscr | Richard Henderson | 1 | -0/+1 |
| 2019-02-18 | target/ppc: Pass integer to helper_mtvscr | Richard Henderson | 1 | -1/+1 |
| 2019-02-18 | target/ppc: convert vsplt[bhw] to use vector operations | Richard Henderson | 1 | -3/+0 |
| 2019-02-18 | target/ppc: convert vspltis[bhw] to use vector operations | Richard Henderson | 1 | -3/+0 |
| 2019-02-18 | target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper... | Mark Cave-Ayland | 1 | -8/+0 |
| 2018-11-08 | target/ppc: add external PID support | Roman Kapl | 1 | -0/+4 |
| 2018-10-18 | target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 | Richard Henderson | 1 | -1/+1 |
| 2018-08-21 | target/ppc: Use non-arithmetic conversions for fp load/store | Richard Henderson | 1 | -2/+2 |
| 2018-08-21 | target/ppc: Tidy helper_fsqrt | Richard Henderson | 1 | -1/+1 |
| 2018-08-21 | target/ppc: Tidy helper_fadd, helper_fsub | Richard Henderson | 1 | -2/+2 |
| 2018-08-21 | target/ppc: Tidy helper_fmul | Richard Henderson | 1 | -1/+1 |
| 2018-08-21 | target/ppc: Honor fpscr_ze semantics and tidy fdiv | Richard Henderson | 1 | -1/+1 |
| 2018-07-03 | target/ppc: Use atomic cmpxchg for STQCX | Richard Henderson | 1 | -0/+2 |
| 2018-07-03 | target/ppc: Use atomic store for STQ | Richard Henderson | 1 | -0/+4 |
| 2018-07-03 | target/ppc: Use atomic load for LQ and LQARX | Richard Henderson | 1 | -0/+5 |
| 2018-06-12 | target/ppc: Allow privileged access to SPR_PCR | Joel Stanley | 1 | -0/+1 |
| 2018-05-04 | target/ppc: add basic support for PTCR on POWER9 | Cédric Le Goater | 1 | -0/+1 |
| 2018-01-20 | target/ppc: add support for hypervisor doorbells on book3s CPUs | Cédric Le Goater | 1 | -0/+2 |
| 2017-04-26 | target/ppc: Flush TLB on write to PIDR | Suraj Jitindar Singh | 1 | -0/+1 |
| 2017-02-22 | target-ppc: Add xscvqpudz and xscvqpuwz instructions | Bharata B Rao | 1 | -0/+2 |
| 2017-02-22 | target-ppc: add slbieg instruction | Nikunj A Dadhania | 1 | -0/+1 |
| 2017-02-22 | target-ppc: Add xsmaxjdp and xsminjdp instructions | Bharata B Rao | 1 | -0/+2 |
| 2017-02-22 | target-ppc: Add xsmaxcdp and xsmincdp instructions | Bharata B Rao | 1 | -0/+2 |
| 2017-02-22 | ppc: implement xssubqp instruction | Jose Ricardo Ziviani | 1 | -0/+1 |
| 2017-02-22 | ppc: implement xssqrtqp instruction | Jose Ricardo Ziviani | 1 | -0/+1 |
| 2017-02-22 | ppc: implement xsrqpxp instruction | Jose Ricardo Ziviani | 1 | -0/+1 |
| 2017-02-22 | ppc: implement xsrqpi[x] instruction | Jose Ricardo Ziviani | 1 | -0/+1 |
| 2017-02-02 | target-ppc: Add xststdc[sp, dp, qp] instructions | Nikunj A Dadhania | 1 | -0/+3 |
