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ppc
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cpu.h
Age
Commit message (
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Author
Files
Lines
2022-05-05
target/ppc: Change MSR_* to follow POWER ISA numbering convention
Víctor Colombo
1
-43
/
+44
2022-05-05
target/ppc: Add unused msr bits FIELDs
Víctor Colombo
1
-0
/
+25
2022-05-05
target/ppc: Remove msr_de macro
Víctor Colombo
1
-2
/
+1
2022-05-05
target/ppc: Remove msr_hv macro
Víctor Colombo
1
-5
/
+6
2022-05-05
target/ppc: Remove msr_ts macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_fe0 and msr_fe1 macros
Víctor Colombo
1
-2
/
+9
2022-05-05
target/ppc: Remove msr_ep macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_dr macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_ir macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_cm macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_fp macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_gs macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_me macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_pow macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_ce macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_ee macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_ile macro
Víctor Colombo
1
-2
/
+2
2022-05-05
target/ppc: Remove msr_ds macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_le macro
Víctor Colombo
1
-1
/
+1
2022-05-05
target/ppc: Remove msr_pr macro
Víctor Colombo
1
-1
/
+3
2022-05-05
target/ppc: Remove unused msr_* macros
Víctor Colombo
1
-20
/
+0
2022-05-05
target/ppc: Remove fpscr_* macros from cpu.h
Víctor Colombo
1
-29
/
+0
2022-04-21
compiler.h: replace QEMU_NORETURN with G_NORETURN
Marc-André Lureau
1
-7
/
+7
2022-04-06
Move CPU softfloat unions to cpu-float.h
Marc-André Lureau
1
-0
/
+1
2022-04-06
Replace config-time define HOST_WORDS_BIGENDIAN
Marc-André Lureau
1
-1
/
+1
2022-03-06
target: Use ArchCPU as interface to target CPU
Philippe Mathieu-Daudé
1
-1
/
+1
2022-03-06
target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
Philippe Mathieu-Daudé
1
-2
/
+0
2022-03-06
target: Use CPUArchState as interface to target-specific CPU state
Philippe Mathieu-Daudé
1
-2
/
+1
2022-03-02
target/ppc: trigger PERFM EBBs from power8-pmu.c
Daniel Henrique Barboza
1
-0
/
+5
2022-03-02
target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions
Daniel Henrique Barboza
1
-1
/
+4
2022-02-18
target/ppc: cpu_init: Move check_pow and QOM macros to a header
Fabiano Rosas
1
-0
/
+39
2022-02-18
target/ppc: Introduce a vhyp framework for nested HV support
Nicholas Piggin
1
-0
/
+7
2022-02-18
target/ppc: make vhyp get_pate method take lpid and return success
Nicholas Piggin
1
-1
/
+2
2022-02-09
target/ppc: Remove PowerPC 601 CPUs
Cédric Le Goater
1
-33
/
+6
2022-01-28
target/ppc: Remove support for the PowerPC 602 CPU
Cédric Le Goater
1
-7
/
+1
2022-01-28
target/ppc: 405: Rename MSR_POW to MSR_WE
Fabiano Rosas
1
-0
/
+1
2022-01-18
target/ppc: Finish removal of 401/403 CPUs
Cédric Le Goater
1
-1
/
+0
2022-01-12
target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian
Fabiano Rosas
1
-1
/
+3
2022-01-12
target/ppc: Add HV support to ppc_interrupts_little_endian
Fabiano Rosas
1
-8
/
+15
2022-01-04
target/ppc: Cache per-pmc insn and cycle count settings
Richard Henderson
1
-0
/
+3
2022-01-04
ppc/ppc405: Restore TCR and STR write handlers
Cédric Le Goater
1
-0
/
+2
2021-12-17
PPC64/TCG: Implement 'rfebb' instruction
Daniel Henrique Barboza
1
-0
/
+13
2021-12-17
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
Daniel Henrique Barboza
1
-0
/
+4
2021-12-17
target/ppc: enable PMU instruction count
Daniel Henrique Barboza
1
-0
/
+1
2021-12-17
target/ppc: enable PMU counter overflow with cycle events
Daniel Henrique Barboza
1
-0
/
+2
2021-12-17
target/ppc: PMU basic cycle count for pseries TCG
Daniel Henrique Barboza
1
-0
/
+20
2021-12-17
target/ppc: introduce PMUEventType and PMU overflow timers
Daniel Henrique Barboza
1
-0
/
+15
2021-12-17
target/ppc: Remove the software TLB model of 7450 CPUs
Fabiano Rosas
1
-3
/
+1
2021-12-17
target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52
Lucas Mateus Castro (alqotel)
1
-0
/
+4
2021-11-02
target/ppc: Implement ppc_cpu_record_sigsegv
Richard Henderson
1
-3
/
+0
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