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2017-12-18misc: remove duplicated includesPhilippe Mathieu-Daudé1-1/+0
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-46/+26
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov2-46/+26
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-3/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+1
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne4-5/+5
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne1-2/+3
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-0/+6
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2-8/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-2/+2
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne5-1/+28
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne2-28/+5
2017-05-04target/openrisc: Implement full vmstate serializationStafford Horne1-2/+71
2017-05-04target/openrisc: implement shadow registersStafford Horne6-10/+33
2017-05-04target/openrisc: add numcores and coreid supportStafford Horne1-0/+6
2017-05-04target/openrisc: Fixes for memory debuggingStafford Horne1-4/+20
2017-04-21target/openrisc: Implement EPH bitTim 'mithro' Ansell1-0/+3
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell4-1/+21
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson3-23/+66
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson5-35/+25
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson6-55/+39
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson1-1/+5
2017-02-14target/openrisc: Fix maddRichard Henderson4-61/+30
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson1-0/+108
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson4-61/+80
2017-02-14target/openrisc: Implement msyncRichard Henderson1-0/+1
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson1-32/+0
2017-02-14target/openrisc: Set flags on helpersRichard Henderson1-12/+12
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson1-14/+14
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson4-89/+78
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson7-74/+96
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson1-207/+95
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson3-12/+18
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson5-314/+191
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson1-58/+40
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson1-24/+12
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson7-8/+81
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne1-0/+7
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson1-1/+1
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée3-3/+3
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-8/+4
2017-01-10target-openrisc: Use clz and ctz opcodesRichard Henderson3-23/+4
2016-12-20Move target-* CPU file into a target/ folderThomas Huth17-0/+3868