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2019-01-30target/openrisc: Fix LGPL version numberThomas Huth7-7/+7
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau1-2/+3
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2-112/+111
2018-07-03target/openrisc: Fix writes to interrupt mask registerStafford Horne1-1/+1
2018-07-03target/openrisc: Fix delay slot exception flag to match specStafford Horne1-7/+12
2018-07-03linux-user: Implement signals for openriscRichard Henderson1-0/+1
2018-07-03target/openrisc: Reorg tlb lookupRichard Henderson2-170/+88
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson3-6/+7
2018-07-03target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson1-30/+5
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson4-18/+16
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson6-32/+49
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson1-6/+15
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson4-32/+30
2018-07-03target/openrisc: Merge mmu_helper.c into mmu.cRichard Henderson3-41/+12
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson7-119/+32
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson6-49/+46
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson3-15/+14
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson1-1/+16
2018-07-03target/openrisc: Split out is_userRichard Henderson1-15/+12
2018-07-03target/openrisc: Link more translation blocksRichard Henderson1-41/+55
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson1-18/+17
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2-5/+4
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson1-4/+0
2018-07-03target/openrisc: Log interruptsRichard Henderson1-5/+25
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson5-115/+179
2018-07-02target/openrisc: Fix mtspr shadow gprsRichard Henderson1-0/+1
2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...Peter Maydell1-3/+3
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé1-1/+0
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson1-9/+4
2018-05-14target/openrisc: Convert dec_floatRichard Henderson2-230/+149
2018-05-14target/openrisc: Convert dec_compiRichard Henderson2-58/+70
2018-05-14target/openrisc: Convert dec_compRichard Henderson2-62/+73
2018-05-14target/openrisc: Convert dec_MRichard Henderson2-28/+16
2018-05-14target/openrisc: Convert dec_logicRichard Henderson2-36/+32
2018-05-14target/openrisc: Convert dec_macRichard Henderson2-33/+27
2018-05-14target/openrisc: Convert dec_calcRichard Henderson2-169/+229
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2-153/+141
2018-05-14target/openrisc: Convert memory insnsRichard Henderson2-139/+160
2018-05-14target/openrisc: Convert branch insnsRichard Henderson2-78/+84
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson3-43/+78
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson3-252/+126
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota1-84/+79
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota1-47/+46
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk1-4/+4
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée2-1/+1
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-3/+2
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier3-8/+8