riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-2/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	2	-11/+20
2019-05-10	tcg: Use CPUClass::tlb_fill in cputlb.c	Richard Henderson	1	-6/+0
2019-05-10	target/openrisc: Convert to CPUClass::tlb_fill	Richard Henderson	3	-36/+39
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth	8	-8/+8
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	1	-2/+2
2019-04-18	disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h	Markus Armbruster	1	-1/+1
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	2	-8/+6
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	2	-11/+6
2019-01-30	target/openrisc: Fix LGPL version number	Thomas Huth	7	-7/+7
2018-11-27	vmstate: constify VMStateField	Marc-André Lureau	1	-2/+3
2018-10-31	decodetree: Remove "insn" argument from trans_* expanders	Richard Henderson	2	-112/+111
2018-07-03	target/openrisc: Fix writes to interrupt mask register	Stafford Horne	1	-1/+1
2018-07-03	target/openrisc: Fix delay slot exception flag to match spec	Stafford Horne	1	-7/+12
2018-07-03	linux-user: Implement signals for openrisc	Richard Henderson	1	-0/+1
2018-07-03	target/openrisc: Reorg tlb lookup	Richard Henderson	2	-170/+88
2018-07-03	target/openrisc: Increase the TLB size	Richard Henderson	3	-6/+7
2018-07-03	target/openrisc: Stub out handle_mmu_fault for softmmu	Richard Henderson	1	-30/+5
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	4	-18/+16
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	6	-32/+49
2018-07-03	target/openrisc: Fix tlb flushing in mtspr	Richard Henderson	1	-6/+15
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	4	-32/+30
2018-07-03	target/openrisc: Merge mmu_helper.c into mmu.c	Richard Henderson	3	-41/+12
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	7	-119/+32
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	6	-49/+46
2018-07-03	target/openrisc: Form the spr index from tcg	Richard Henderson	3	-15/+14
2018-07-03	target/openrisc: Exit the TB after l.mtspr	Richard Henderson	1	-1/+16
2018-07-03	target/openrisc: Split out is_user	Richard Henderson	1	-15/+12
2018-07-03	target/openrisc: Link more translation blocks	Richard Henderson	1	-41/+55
2018-07-03	target/openrisc: Fix singlestep_enabled	Richard Henderson	1	-18/+17
2018-07-03	target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB	Richard Henderson	2	-5/+4
2018-07-03	target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP	Richard Henderson	1	-4/+0
2018-07-03	target/openrisc: Log interrupts	Richard Henderson	1	-5/+25
2018-07-03	target/openrisc: Add print_insn_or1k	Richard Henderson	5	-115/+179
2018-07-02	target/openrisc: Fix mtspr shadow gprs	Richard Henderson	1	-0/+1
2018-06-04	Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...	Peter Maydell	1	-3/+3
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	1	-3/+3
2018-06-01	target: Do not include "exec/exec-all.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-05-14	target/openrisc: Merge disas_openrisc_insn	Richard Henderson	1	-9/+4
2018-05-14	target/openrisc: Convert dec_float	Richard Henderson	2	-230/+149
2018-05-14	target/openrisc: Convert dec_compi	Richard Henderson	2	-58/+70
2018-05-14	target/openrisc: Convert dec_comp	Richard Henderson	2	-62/+73
2018-05-14	target/openrisc: Convert dec_M	Richard Henderson	2	-28/+16
2018-05-14	target/openrisc: Convert dec_logic	Richard Henderson	2	-36/+32
2018-05-14	target/openrisc: Convert dec_mac	Richard Henderson	2	-33/+27
2018-05-14	target/openrisc: Convert dec_calc	Richard Henderson	2	-169/+229
2018-05-14	target/openrisc: Convert remainder of dec_misc insns	Richard Henderson	2	-153/+141
2018-05-14	target/openrisc: Convert memory insns	Richard Henderson	2	-139/+160
2018-05-14	target/openrisc: Convert branch insns	Richard Henderson	2	-78/+84