riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	5	-1/+28
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne	2	-28/+5
2017-05-04	target/openrisc: Implement full vmstate serialization	Stafford Horne	1	-2/+71
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	6	-10/+33
2017-05-04	target/openrisc: add numcores and coreid support	Stafford Horne	1	-0/+6
2017-05-04	target/openrisc: Fixes for memory debugging	Stafford Horne	1	-4/+20
2017-04-21	target/openrisc: Implement EPH bit	Tim 'mithro' Ansell	1	-0/+3
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	4	-1/+21
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson	3	-23/+66
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	5	-35/+25
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	6	-55/+39
2017-02-14	target/openrisc: Optimize l.jal to next	Richard Henderson	1	-1/+5
2017-02-14	target/openrisc: Fix madd	Richard Henderson	4	-61/+30
2017-02-14	target/openrisc: Implement muld, muldu, macu, msbu	Richard Henderson	1	-0/+108
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	4	-61/+80
2017-02-14	target/openrisc: Implement msync	Richard Henderson	1	-0/+1
2017-02-14	target/openrisc: Enable trap, csync, msync, psync for user mode	Richard Henderson	1	-32/+0
2017-02-14	target/openrisc: Set flags on helpers	Richard Henderson	1	-12/+12
2017-02-14	target/openrisc: Use movcond where appropriate	Richard Henderson	1	-14/+14
2017-02-14	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson	4	-89/+78
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	7	-74/+96
2017-02-14	target/openrisc: Invert the decoding in dec_calc	Richard Henderson	1	-207/+95
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	3	-12/+18
2017-02-14	target/openrisc: Streamline arithmetic and OVE	Richard Henderson	5	-314/+191
2017-02-14	target/openrisc: Rationalize immediate extraction	Richard Henderson	1	-58/+40
2017-02-14	target/openrisc: Tidy insn dumping	Richard Henderson	1	-24/+12
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	7	-8/+81
2017-02-14	target/openrisc: Fix exception handling status registers	Stafford Horne	1	-0/+7
2017-02-14	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson	1	-1/+1
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	3	-3/+3
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	2	-8/+4
2017-01-10	target-openrisc: Use clz and ctz opcodes	Richard Henderson	3	-23/+4
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	17	-0/+3868