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path: root/target/openrisc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-1/+1
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-42/+42
2023-08-31target/translate: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé1-1/+0
2023-08-24target/openrisc: Use tcg_gen_negsetcond_*Richard Henderson1-4/+2
2023-07-25other architectures: spelling fixesMichael Tokarev1-2/+2
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-6/+3
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
2023-05-11target/openrisc: Allow fpcsr access in user modeStafford Horne1-40/+32
2023-03-05target/openrisc: Drop tcg_temp_freeRichard Henderson1-39/+0
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2022-10-26target/openrisc: Convert to tcg_ops restore_state_to_opcRichard Henderson1-10/+0
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+4
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2021-10-15target/openrisc: Drop checks for singlestep_enabledRichard Henderson1-15/+3
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-1/+1
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-17/+0
2021-07-13target/openrisc: Use dc->zero in gen_add, gen_addcRichard Henderson1-5/+5
2021-07-13target/openrisc: Cache constant 0 in DisasContextRichard Henderson1-6/+6
2021-07-13target/openrisc: Use tcg_constant_tl for dc->R0Richard Henderson1-8/+2
2021-07-13target/openrisc: Use tcg_constant_*Richard Henderson1-33/+9
2021-07-09target/openrisc: Use translator_use_goto_tbRichard Henderson1-7/+8
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé1-1/+0
2021-04-01target/openrisc: fix icount handling for timer instructionsPavel Dovgalyuk1-0/+15
2020-08-21meson: targetPaolo Bonzini1-1/+1
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-10-28target/openrisc: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-09-04target/openrisc: Implement l.adrpRichard Henderson1-0/+13
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson1-0/+85
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson1-0/+230
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson1-49/+35
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson1-7/+12
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson1-97/+116
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson1-47/+49
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-2/+2
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-6/+5
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth1-1/+1
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson1-100/+100
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson1-1/+1
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson1-7/+9
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson1-1/+16
2018-07-03target/openrisc: Split out is_userRichard Henderson1-15/+12
2018-07-03target/openrisc: Link more translation blocksRichard Henderson1-41/+55
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson1-18/+17
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson1-3/+3
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson1-4/+0
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson1-114/+0
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3