riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-02-14	target/openrisc: Optimize l.jal to next	Richard Henderson	1	-1/+5
2017-02-14	target/openrisc: Fix madd	Richard Henderson	1	-9/+4
2017-02-14	target/openrisc: Implement muld, muldu, macu, msbu	Richard Henderson	1	-0/+108
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	1	-57/+63
2017-02-14	target/openrisc: Implement msync	Richard Henderson	1	-0/+1
2017-02-14	target/openrisc: Enable trap, csync, msync, psync for user mode	Richard Henderson	1	-32/+0
2017-02-14	target/openrisc: Use movcond where appropriate	Richard Henderson	1	-14/+14
2017-02-14	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson	1	-79/+40
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-64/+40
2017-02-14	target/openrisc: Invert the decoding in dec_calc	Richard Henderson	1	-207/+95
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	1	-9/+15
2017-02-14	target/openrisc: Streamline arithmetic and OVE	Richard Henderson	1	-249/+177
2017-02-14	target/openrisc: Rationalize immediate extraction	Richard Henderson	1	-58/+40
2017-02-14	target/openrisc: Tidy insn dumping	Richard Henderson	1	-24/+12
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	1	-0/+58
2017-01-10	target-openrisc: Use clz and ctz opcodes	Richard Henderson	1	-2/+4
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+1783