index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
openrisc
/
translate.c
Age
Commit message (
Expand
)
Author
Files
Lines
2019-10-28
target/openrisc: fetch code with translator_ld
Emilio G. Cota
1
-1
/
+1
2019-09-04
target/openrisc: Implement l.adrp
Richard Henderson
1
-0
/
+13
2019-09-04
target/openrisc: Implement unordered fp comparisons
Richard Henderson
1
-0
/
+85
2019-09-04
target/openrisc: Add support for ORFPX64A32
Richard Henderson
1
-0
/
+230
2019-09-04
target/openrisc: Check CPUCFG_OF32S for float insns
Richard Henderson
1
-49
/
+35
2019-09-04
target/openrisc: Cache R0 in DisasContext
Richard Henderson
1
-7
/
+12
2019-09-04
target/openrisc: Replace cpu register array with a function
Richard Henderson
1
-97
/
+116
2019-09-04
target/openrisc: Add DisasContext parameter to check_r0_write
Richard Henderson
1
-47
/
+49
2019-09-03
tcg: TCGMemOp is now accelerator independent MemOp
Tony Nguyen
1
-2
/
+2
2019-06-12
Include qemu-common.h exactly where needed
Markus Armbruster
1
-1
/
+0
2019-04-24
tcg: Hoist max_insns computation to tb_gen_code
Richard Henderson
1
-2
/
+2
2019-04-18
qom/cpu: Simplify how CPUClass:cpu_dump_state() prints
Markus Armbruster
1
-6
/
+5
2019-01-30
target/openrisc: Fix LGPL version number
Thomas Huth
1
-1
/
+1
2018-10-31
decodetree: Remove "insn" argument from trans_* expanders
Richard Henderson
1
-100
/
+100
2018-07-03
target/openrisc: Fix cpu_mmu_index
Richard Henderson
1
-1
/
+1
2018-07-03
target/openrisc: Form the spr index from tcg
Richard Henderson
1
-7
/
+9
2018-07-03
target/openrisc: Exit the TB after l.mtspr
Richard Henderson
1
-1
/
+16
2018-07-03
target/openrisc: Split out is_user
Richard Henderson
1
-15
/
+12
2018-07-03
target/openrisc: Link more translation blocks
Richard Henderson
1
-41
/
+55
2018-07-03
target/openrisc: Fix singlestep_enabled
Richard Henderson
1
-18
/
+17
2018-07-03
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Richard Henderson
1
-3
/
+3
2018-07-03
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
Richard Henderson
1
-4
/
+0
2018-07-03
target/openrisc: Add print_insn_or1k
Richard Henderson
1
-114
/
+0
2018-06-01
tcg: Pass tb and index to tcg_gen_exit_tb separately
Richard Henderson
1
-3
/
+3
2018-05-14
target/openrisc: Merge disas_openrisc_insn
Richard Henderson
1
-9
/
+4
2018-05-14
target/openrisc: Convert dec_float
Richard Henderson
1
-230
/
+128
2018-05-14
target/openrisc: Convert dec_compi
Richard Henderson
1
-58
/
+58
2018-05-14
target/openrisc: Convert dec_comp
Richard Henderson
1
-62
/
+58
2018-05-14
target/openrisc: Convert dec_M
Richard Henderson
1
-28
/
+13
2018-05-14
target/openrisc: Convert dec_logic
Richard Henderson
1
-36
/
+26
2018-05-14
target/openrisc: Convert dec_mac
Richard Henderson
1
-33
/
+22
2018-05-14
target/openrisc: Convert dec_calc
Richard Henderson
1
-149
/
+173
2018-05-14
target/openrisc: Convert remainder of dec_misc insns
Richard Henderson
1
-149
/
+110
2018-05-14
target/openrisc: Convert memory insns
Richard Henderson
1
-139
/
+136
2018-05-14
target/openrisc: Convert branch insns
Richard Henderson
1
-78
/
+72
2018-05-14
target/openrisc: Start conversion to decodetree.py
Richard Henderson
1
-43
/
+41
2018-05-14
target-openrisc: Write back result before FPE exception
Richard Henderson
1
-36
/
+65
2018-05-09
target/openrisc: convert to TranslatorOps
Emilio G. Cota
1
-84
/
+79
2018-05-09
target/openrisc: convert to DisasContextBase
Emilio G. Cota
1
-47
/
+46
2017-10-27
Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging
Peter Maydell
1
-1
/
+1
2017-10-25
disas: Remove unused flags arguments
Richard Henderson
1
-1
/
+1
2017-10-24
tcg: Initialize cpu_env generically
Richard Henderson
1
-3
/
+0
2017-10-24
tcg: define tcg_init_ctx and make tcg_ctx a pointer
Emilio G. Cota
1
-1
/
+1
2017-10-24
tcg: convert tb->cflags reads to tb_cflags(tb)
Emilio G. Cota
1
-3
/
+3
2017-09-06
target: [tcg] Use a generic enum for DISAS_ values
Lluís Vilanova
1
-0
/
+6
2017-07-19
tcg: Pass generic CPUState to gen_intermediate_code()
Lluís Vilanova
1
-2
/
+2
2017-05-04
target/openrisc: implement shadow registers
Stafford Horne
1
-2
/
+3
2017-02-14
target/openrisc: Optimize for r0 being zero
Richard Henderson
1
-22
/
+61
2017-02-14
target/openrisc: Tidy handling of delayed branches
Richard Henderson
1
-24
/
+16
2017-02-14
target/openrisc: Tidy ppc/npc implementation
Richard Henderson
1
-18
/
+11
[next]