riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-05-02	Do not include sysemu/sysemu.h if it's not really necessary	Thomas Huth	1	-1/+0
2020-11-17	target/openrisc: Remove dead code attempting to check "is timer disabled"	Peter Maydell	1	-3/+0
2019-09-04	target/openrisc: Implement move to/from FPCSR	Richard Henderson	1	-5/+11
2019-09-04	target/openrisc: Add VR2 and AVR special processor registers	Richard Henderson	1	-0/+6
2019-09-04	target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init	Richard Henderson	1	-2/+2
2019-09-04	target/openrisc: Make VR and PPC read-only	Richard Henderson	1	-9/+1
2019-07-05	general: Replace global smp variables with smp machine properties	Like Xu	1	-1/+5
2019-06-10	target/openrisc: Use env_cpu, env_archcpu	Richard Henderson	1	-4/+4
2019-01-30	target/openrisc: Fix LGPL version number	Thomas Huth	1	-1/+1
2018-07-03	target/openrisc: Fix writes to interrupt mask register	Stafford Horne	1	-1/+1
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	1	-8/+8
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	1	-4/+0
2018-07-03	target/openrisc: Fix tlb flushing in mtspr	Richard Henderson	1	-6/+15
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	1	-10/+10
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	1	-15/+0
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	1	-14/+14
2018-07-03	target/openrisc: Form the spr index from tcg	Richard Henderson	1	-6/+3
2018-07-02	target/openrisc: Fix mtspr shadow gprs	Richard Henderson	1	-0/+1
2018-04-11	icount: fix cpu_restore_state_from_tb for non-tb-exit cases	Pavel Dovgalyuk	1	-4/+4
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	1	-2/+2
2017-10-21	target/openrisc: Make coreid and numcores variable	Stafford Horne	1	-2/+3
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+13
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	1	-0/+9
2017-05-04	target/openrisc: add numcores and coreid support	Stafford Horne	1	-0/+6
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	1	-0/+7
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	1	-1/+1
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	1	-28/+16
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	1	-0/+13
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-3/+2
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+288