| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-10-21 | openrisc/cputimer: Perparation for Multicore | Stafford Horne | 1 | -1/+0 |
| 2017-05-04 | target/openrisc: Support non-busy idle state using PMR SPR | Stafford Horne | 1 | -0/+1 |
| 2017-05-04 | target/openrisc: Implement full vmstate serialization | Stafford Horne | 1 | -2/+71 |
| 2017-05-04 | target/openrisc: implement shadow registers | Stafford Horne | 1 | -3/+3 |
| 2017-02-14 | target/openrisc: Tidy ppc/npc implementation | Richard Henderson | 1 | -3/+2 |
| 2017-02-14 | target/openrisc: Represent MACHI:MACLO as a single unit | Richard Henderson | 1 | -2/+3 |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 1 | -1/+37 |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson | 1 | -8/+16 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+54 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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