| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-01-30 | target/openrisc: Fix LGPL version number | Thomas Huth | 1 | -1/+1 |
| 2018-07-03 | target/openrisc: Fix cpu_mmu_index | Richard Henderson | 1 | -12/+3 |
| 2018-07-03 | target/openrisc: Remove indirect function calls for mmu | Richard Henderson | 1 | -22/+3 |
| 2018-07-03 | target/openrisc: Merge tlb allocation into CPUOpenRISCState | Richard Henderson | 1 | -4/+4 |
| 2018-07-03 | target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB | Richard Henderson | 1 | -2/+1 |
| 2017-02-14 | target/openrisc: Tidy ppc/npc implementation | Richard Henderson | 1 | -1/+0 |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 1 | -1/+1 |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson | 1 | -0/+1 |
| 2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 1 | -1/+1 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+60 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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