riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-07-31	target/openrisc: Set EPCR to next PC on FPE exceptions	Stafford Horne	1	-3/+4
2023-03-07	gdbstub: move register helpers into standalone include	Alex Bennée	1	-1/+1
2022-09-04	target/openrisc: Add interrupted CPU to log	Stafford Horne	1	-1/+3
2022-02-21	exec/exec-all: Move 'qemu/log.h' include in units requiring it	Philippe Mathieu-Daudé	1	-0/+1
2021-09-14	target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	1	-2/+0
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth	1	-1/+1
2018-07-03	target/openrisc: Fix delay slot exception flag to match spec	Stafford Horne	1	-7/+12
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	1	-4/+0
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	1	-2/+0
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	1	-2/+2
2018-07-03	target/openrisc: Log interrupts	Richard Henderson	1	-5/+25
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+2
2017-04-21	target/openrisc: Implement EPH bit	Tim 'mithro' Ansell	1	-0/+3
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	1	-1/+5
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	1	-2/+2
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-1/+1
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	1	-0/+1
2017-02-14	target/openrisc: Fix exception handling status registers	Stafford Horne	1	-0/+7
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+87