| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-09-04 | target/openrisc: Implement unordered fp comparisons | Richard Henderson | 1 | -0/+4 |
| 2019-09-04 | target/openrisc: Add support for ORFPX64A32 | Richard Henderson | 1 | -0/+2 |
| 2019-01-30 | target/openrisc: Fix LGPL version number | Thomas Huth | 1 | -1/+1 |
| 2018-07-03 | target/openrisc: Form the spr index from tcg | Richard Henderson | 1 | -2/+2 |
| 2018-05-14 | target-openrisc: Write back result before FPE exception | Richard Henderson | 1 | -13/+12 |
| 2017-02-14 | target/openrisc: Fix madd | Richard Henderson | 1 | -5/+2 |
| 2017-02-14 | target/openrisc: Set flags on helpers | Richard Henderson | 1 | -12/+12 |
| 2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson | 1 | -1/+3 |
| 2017-02-14 | target/openrisc: Streamline arithmetic and OVE | Richard Henderson | 1 | -3/+1 |
| 2017-01-10 | target-openrisc: Use clz and ctz opcodes | Richard Henderson | 1 | -2/+0 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+66 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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