riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-2/+0
2021-09-14	target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	1	-2/+3
2020-12-15	target/openrisc: Move pic_cpu code into CPU object proper	Peter Maydell	1	-1/+0
2020-09-18	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	Eduardo Habkost	1	-1/+1
2020-09-09	Use OBJECT_DECLARE_TYPE where possible	Eduardo Habkost	1	-4/+2
2020-09-09	Use DECLARE_CHECKER macros	Eduardo Habkost	1	-6/+2
2020-09-09	Move QOM typedefs and add missing includes	Eduardo Habkost	1	-4/+7
2020-03-19	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell	1	-1/+1
2020-03-17	cpu: Use DeviceClass reset instead of a special CPUClass reset	Peter Maydell	1	-1/+1
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée	1	-1/+1
2019-09-04	target/openrisc: Implement move to/from FPCSR	Richard Henderson	1	-0/+2
2019-09-04	target/openrisc: Add VR2 and AVR special processor registers	Richard Henderson	1	-4/+7
2019-09-04	target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init	Richard Henderson	1	-4/+4
2019-09-04	target/openrisc: Make VR and PPC read-only	Richard Henderson	1	-3/+0
2019-08-21	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster	1	-1/+1
2019-08-16	migration: Move the VMStateDescription typedef to typedefs.h	Markus Armbruster	1	-1/+1
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson	1	-2/+0
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson	1	-1/+1
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson	1	-1/+0
2019-06-10	target/openrisc: Use env_cpu, env_archcpu	Richard Henderson	1	-5/+0
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	1	-2/+0
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-2/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	1	-11/+3
2019-05-10	target/openrisc: Convert to CPUClass::tlb_fill	Richard Henderson	1	-2/+3
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth	1	-1/+1
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-2/+1
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-1/+1
2018-07-03	target/openrisc: Reorg tlb lookup	Richard Henderson	1	-8/+0
2018-07-03	target/openrisc: Increase the TLB size	Richard Henderson	1	-1/+1
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	1	-6/+4
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	1	-8/+15
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	1	-4/+2
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	1	-11/+0
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	1	-2/+4
2018-07-03	target/openrisc: Add print_insn_or1k	Richard Henderson	1	-0/+1
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov	1	-2/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-1/+0
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-1/+1
2017-10-27	openrisc: cleanup cpu type name composition	Igor Mammedov	1	-0/+3
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	1	-1/+3
2017-09-01	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov	1	-3/+1
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+10
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne	1	-14/+2
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	1	-2/+13
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	1	-0/+7
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson	1	-1/+4
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	1	-7/+5