Age | Commit message (Expand) | Author | Files | Lines |
2019-01-24 | target/mips: Add I6500 core configuration | Yongbok Kim | 1 | -0/+40 |
2019-01-24 | target/mips: nanoMIPS: Fix branch handling | Stefan Markovic | 1 | -0/+12 |
2019-01-24 | target/mips: Extend gen_scwp() functionality to support EVA | Aleksandar Markovic | 1 | -4/+6 |
2019-01-24 | target/mips: Correct the second argument type of cpu_supports_isa() | Aleksandar Markovic | 2 | -2/+2 |
2019-01-24 | target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers | Aleksandar Markovic | 1 | -13/+13 |
2019-01-24 | target/mips: nanoMIPS: Remove an unused macro | Aleksandar Markovic | 1 | -1/+0 |
2019-01-24 | target/mips: nanoMIPS: Remove duplicate macro definitions | Aleksandar Markovic | 1 | -10/+0 |
2019-01-18 | target/mips: Introduce 32 R5900 multimedia registers | Fredrik Noring | 2 | -0/+19 |
2019-01-18 | target/mips: Rename 'rn' to 'register_name' | Aleksandar Markovic | 1 | -426/+432 |
2019-01-18 | target/mips: Add CP0 register MemoryMapID | Aleksandar Markovic | 2 | -2/+4 |
2019-01-18 | target/mips: Amend preprocessor constants for CP0 registers | Aleksandar Markovic | 2 | -170/+284 |
2019-01-18 | target/mips: Update ITU to utilize SAARI and SAAR CP0 registers | Yongbok Kim | 2 | -0/+19 |
2019-01-18 | target/mips: Provide R/W access to SAARI and SAAR CP0 registers | Yongbok Kim | 5 | -4/+120 |
2019-01-18 | target/mips: Add fields for SAARI and SAAR CP0 registers | Yongbok Kim | 2 | -4/+12 |
2019-01-18 | target/mips: Use preprocessor constants for 32 major CP0 registers | Aleksandar Markovic | 1 | -136/+136 |
2019-01-18 | target/mips: Add preprocessor constants for 32 major CP0 registers | Aleksandar Markovic | 1 | -0/+32 |
2019-01-18 | target/mips: Move comment containing summary of CP0 registers | Aleksandar Markovic | 1 | -81/+84 |
2019-01-11 | avoid TABs in files that only contain a few | Paolo Bonzini | 1 | -1/+1 |
2019-01-03 | target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions | Fredrik Noring | 1 | -3/+9 |
2019-01-03 | target/mips: Support R5900 three-operand MADD and MADDU instructions | Philippe Mathieu-Daudé | 1 | -5/+53 |
2019-01-03 | target/mips: MXU: Add handler for an align instruction | Aleksandar Markovic | 1 | -3/+194 |
2019-01-03 | target/mips: MXU: Add handlers for max/min instructions | Aleksandar Markovic | 1 | -21/+279 |
2019-01-03 | target/mips: MXU: Add handlers for logic instructions | Aleksandar Markovic | 1 | -34/+205 |
2019-01-03 | target/mips: MXU: Improve the comment containing MXU overview | Aleksandar Markovic | 1 | -30/+44 |
2019-01-03 | target/mips: MXU: Add generic naming for optn2 constants | Aleksandar Markovic | 1 | -0/+5 |
2019-01-03 | target/mips: MXU: Add missing opcodes/decoding for LX* instructions | Aleksandar Markovic | 1 | -38/+102 |
2018-11-27 | vmstate: constify VMStateField | Marc-André Lureau | 1 | -6/+8 |
2018-11-17 | target/mips: Disable R5900 support | Aleksandar Markovic | 1 | -59/+0 |
2018-11-17 | target/mips: Rename MMI-related functions | Aleksandar Markovic | 1 | -16/+16 |
2018-11-17 | target/mips: Rename MMI-related opcodes | Aleksandar Markovic | 1 | -236/+236 |
2018-11-17 | target/mips: Rename MMI-related masks | Aleksandar Markovic | 1 | -10/+10 |
2018-11-17 | target/mips: Guard check_insn with INSN_R5900 check | Fredrik Noring | 1 | -3/+6 |
2018-11-17 | target/mips: Guard check_insn_opc_user_only with INSN_R5900 check | Fredrik Noring | 1 | -4/+12 |
2018-11-17 | target/mips: Fix decoding mechanism of special R5900 opcodes | Fredrik Noring | 1 | -4/+50 |
2018-11-17 | target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 | Fredrik Noring | 1 | -6/+59 |
2018-11-17 | target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 | Fredrik Noring | 1 | -11/+40 |
2018-10-29 | target/mips: Amend MXU ASE overview note | Aleksandar Markovic | 1 | -10/+74 |
2018-10-29 | target/mips: Move MXU_EN check one level higher | Aleksandar Markovic | 1 | -271/+238 |
2018-10-29 | target/mips: Add emulation of MXU instructions S32LDD and S32LDDR | Craig Janeczek | 1 | -7/+47 |
2018-10-29 | target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU | Craig Janeczek | 1 | -7/+94 |
2018-10-29 | target/mips: Add emulation of MXU instruction D16MAC | Craig Janeczek | 1 | -3/+87 |
2018-10-29 | target/mips: Add emulation of MXU instruction D16MUL | Craig Janeczek | 1 | -3/+63 |
2018-10-29 | target/mips: Add emulation of MXU instruction S8LDD | Craig Janeczek | 1 | -3/+87 |
2018-10-29 | target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch | Aleksandar Markovic | 1 | -18/+23 |
2018-10-29 | target/mips: Add emulation of MXU instructions S32I2M and S32M2I | Craig Janeczek | 1 | -6/+85 |
2018-10-29 | target/mips: Add emulation of non-MXU MULL within MXU decoding engine | Craig Janeczek | 1 | -1/+18 |
2018-10-29 | target/mips: Add bit encoding for MXU operand getting pattern 'optn3' | Craig Janeczek | 1 | -0/+10 |
2018-10-29 | target/mips: Add bit encoding for MXU operand getting pattern 'optn2' | Craig Janeczek | 1 | -0/+6 |
2018-10-29 | target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' | Aleksandar Markovic | 1 | -0/+6 |
2018-10-29 | target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' | Craig Janeczek | 1 | -0/+6 |