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2022-05-11Normalize header guard symbol definitionMarkus Armbruster1-1/+1
We commonly define the header guard symbol without an explicit value. Normalize the exceptions. Done with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-26target/mips: Remove stale TODO fileThomas Huth1-51/+0
The last change to this file has been done in 2012, so it seems like this is not really used anymore, and the content is likely very out of date now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220412113824.297108-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-8/+9
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau2-7/+7
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau3-29/+29
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-29target/mips: Fix address space range declaration on n32WANG Xuerui1-1/+1
This bug is probably lurking there for so long, I cannot even git-blame my way to the commit first introducing it. Anyway, because n32 is also TARGET_MIPS64, the address space range cannot be determined by looking at TARGET_MIPS64 alone. Fix this by only declaring 48-bit address spaces for n64, or the n32 user emulation will happily hand out memory ranges beyond the 31-bit limit and crash. Confirmed to make the minimal reproducing example in the linked issue behave. Closes: https://gitlab.com/qemu-project/qemu/-/issues/939 Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: WANG Xuerui <xen0n@gentoo.org> Tested-by: Andreas K. Huettel <dilfridge@gentoo.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220328035942.3299661-1-xen0n@gentoo.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-09Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell3-19/+10
MIPS patches queue - Fix CP0 cycle counter timing - Fix VMState of gt64120 IRQs - Long due PIIX4 QOM cleanups - ISA IRQ QOM'ification / cleanups # gpg: Signature made Tue 08 Mar 2022 18:39:42 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20220308: tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag hw/isa: Inline and remove one-line isa_init_irq() hw/isa: Drop unused attributes from ISADevice hw/isa/isa-bus: Remove isabus_dev_print() hw/input/pckbd: QOM'ify IRQ numbers hw/rtc/m48t59-isa: QOM'ify IRQ number hw/rtc/mc146818rtc: QOM'ify IRQ number hw/mips/gt64xxx_pci: Resolve gt64120_register() hw/isa/piix4: Replace some magic IRQ constants hw/isa/piix4: Resolve global instance variable hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() hw/isa/piix4: Resolve redundant i8259[] attribute malta: Move PCI interrupt handling from gt64xxx_pci to piix4 hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration target/mips: Remove duplicated MIPSCPU::cp0_count_rate target/mips: Fix cycle counter timing calculations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-07target/mips: Remove duplicated MIPSCPU::cp0_count_ratePhilippe Mathieu-Daudé3-19/+9
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle counter timing calculations"), MIPSCPU::cp0_count_rate is not used anymore. We don't need it since it is already expressed as mips_def_t::CCRes. Remove the duplicate and clean. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
2022-03-07target/mips: Fix cycle counter timing calculationsSimon Burge1-1/+2
The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT constant in target/mips/cpu.c. The cycle counter resolution is defined per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating cp0_count_ns. Fixings timing problems on guest OSs for the 20Kc CPU which has a CCRes of 1. Signed-off-by: Simon Burge <simonb@NetBSD.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211213135125.18378-1-simonb@NetBSD.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-15-f4bug@amsat.org>
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2-4/+1
Replace the boilerplate code to declare CPU QOM types and macros, and forward-declare the CPU instance type. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-14-f4bug@amsat.org>
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-4/+2
While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
2022-03-06target: Use forward declared type instead of structure typePhilippe Mathieu-Daudé1-7/+7
The CPU / CPU state are forward declared. $ git grep -E 'struct [A-Za-z]+CPU\ \*' target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); target/openrisc/cpu.h:234: int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, target/openrisc/cpu.h:238: int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, $ git grep -E 'struct CPU[A-Za-z0-9]+State\ \*' target/mips/internal.h:137: int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, target/mips/internal.h:139: void (*helper_tlbwi)(struct CPUMIPSState *env); target/mips/internal.h:140: void (*helper_tlbwr)(struct CPUMIPSState *env); target/mips/internal.h:141: void (*helper_tlbp)(struct CPUMIPSState *env); target/mips/internal.h:142: void (*helper_tlbr)(struct CPUMIPSState *env); target/mips/internal.h:143: void (*helper_tlbinv)(struct CPUMIPSState *env); target/mips/internal.h:144: void (*helper_tlbinvf)(struct CPUMIPSState *env); target/xtensa/cpu.h:347: struct CPUXtensaState *env; ... Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-12-f4bug@amsat.org>
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé1-0/+1
These target-specific files use the target-specific CPU state but lack to include "cpu.h"; i.e.: ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState' void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, ^ ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State' void mmu_flip_um(CPUNios2State *env, unsigned int um); ^ ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'; did you mean 'CPUState'? uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); ^~~~~~~~~~ CPUState Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-10-f4bug@amsat.org>
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé3-0/+3
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson3-8/+24
Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson4-5/+16
Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot3-38/+38
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-11-02Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into stagingRichard Henderson4-2087/+845
MIPS patches queue - Fine-grained MAINTAINERS sections - Fix MSA MADDV.B / MSUBV.B opcodes - Convert MSA opcodes to decodetree - Correct Loongson-3A4000 MSAIR register - Do not accept ELF nanoMIPS binaries on linux-user - Use ISA instead of PCI interrupts in VT82C686 PCI device # gpg: Signature made Tue 02 Nov 2021 09:41:04 AM EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * remotes/philmd/tags/mips-20211102: (41 commits) Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts usb/uhci: Replace pci_set_irq with qemu_set_irq usb/uhci: Disallow user creating a vt82c686-uhci-pci device usb/uhci: Misc clean up target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU target/mips: Fix Loongson-3A4000 MSAIR config register target/mips: Remove one MSA unnecessary decodetree overlap group target/mips: Remove generic MSA opcode target/mips: Convert CTCMSA opcode to decodetree target/mips: Convert CFCMSA opcode to decodetree target/mips: Convert MSA MOVE.V opcode to decodetree target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree target/mips: Convert MSA COPY_U opcode to decodetree target/mips: Convert MSA ELM instruction format to decodetree target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé1-1/+0
FCR0_HAS2008 flag has been enabled in commit ba5c79f2622 ("target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs"), so remove the obsolete FIXME comment. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028212103.2126176-1-f4bug@amsat.org>
2021-11-02target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé1-0/+1
When using the Loongson-3A4000 CPU, the MSAIR is returned with a zero value (because unimplemented). Checking on real hardware, this value appears incorrect: $ cat /proc/cpuinfo system type : generic-loongson-machine machine : loongson,generic cpu model : Loongson-3 V0.4 FPU V0.1 model name : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 ASEs implemented : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2 ... Checking the CFCMSA opcode result with gdb we get 0x60140: Breakpoint 1, 0x00000001200037c4 in main () 1: x/i $pc => 0x1200037c4 <main+52>: cfcmsa v0,msa_ir (gdb) si 0x00000001200037c8 in main () (gdb) i r v0 v0: 0x60140 MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12, so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000 CPU model added in commit af868995e1b. Cc: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026180920.1085516-1-f4bug@amsat.org>
2021-11-02target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé1-182/+180
Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-32-f4bug@amsat.org>
2021-11-02target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé2-9/+0
All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>
2021-11-02target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé2-58/+16
Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-30-f4bug@amsat.org>
2021-11-02target/mips: Convert CFCMSA opcode to decodetreePhilippe Mathieu-Daudé2-9/+23
Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA MOVE.V opcode to decodetreePhilippe Mathieu-Daudé2-6/+20
Convert the MOVE.V opcode (Vector Move) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-28-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA COPY_S and INSERT opcodes to decodetreePhilippe Mathieu-Daudé2-88/+19
Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-27-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA COPY_U opcode to decodetreePhilippe Mathieu-Daudé2-26/+41
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree. Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-26-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA ELM instruction format to decodetreePhilippe Mathieu-Daudé2-13/+52
Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-25-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)Philippe Mathieu-Daudé2-863/+106
Convert 3-register operations to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-24-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé2-34/+9
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé2-158/+35
Convert 3-register operations to decodetree. Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé2-12/+11
Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2-176/+76
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2-39/+38
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-19-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2-75/+31
Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-18-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2-75/+19
Convert 2-register operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2-12/+21
Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2-85/+53
Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-15-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2-59/+36
Convert load/store instructions to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-14-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2-56/+27
Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-13-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2-17/+22
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-12-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2-97/+101
Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-11-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2-77/+41
Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-10-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2-9/+21
Convert the LDI opcode (Immediate Load) to decodetree. Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-9-f4bug@amsat.org>
2021-11-02target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2-18/+17
This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3) and @bz_df -> @bz (generic @bz). Since we modify &msa_bz, re-align its arguments, so the other structures added in the following commits stay visually aligned. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>
2021-11-02target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé1-3/+3
Replace magic DataFormat value by the corresponding enum from CPUMIPSMSADataFormat. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-7-f4bug@amsat.org>
2021-11-02target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé1-7/+18
Have check_msa_access() return a boolean value so we can return early if MSA is not enabled (the instruction got decoded properly, but we raised an exception). Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>
generated by cgit v1.1 at 2024-09-30 11:20:00 +0000