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Author
Files
Lines
2019-01-11
avoid TABs in files that only contain a few
Paolo Bonzini
1
-1
/
+1
2019-01-03
target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
Fredrik Noring
1
-3
/
+9
2019-01-03
target/mips: Support R5900 three-operand MADD and MADDU instructions
Philippe Mathieu-Daudé
1
-5
/
+53
2019-01-03
target/mips: MXU: Add handler for an align instruction
Aleksandar Markovic
1
-3
/
+194
2019-01-03
target/mips: MXU: Add handlers for max/min instructions
Aleksandar Markovic
1
-21
/
+279
2019-01-03
target/mips: MXU: Add handlers for logic instructions
Aleksandar Markovic
1
-34
/
+205
2019-01-03
target/mips: MXU: Improve the comment containing MXU overview
Aleksandar Markovic
1
-30
/
+44
2019-01-03
target/mips: MXU: Add generic naming for optn2 constants
Aleksandar Markovic
1
-0
/
+5
2019-01-03
target/mips: MXU: Add missing opcodes/decoding for LX* instructions
Aleksandar Markovic
1
-38
/
+102
2018-11-27
vmstate: constify VMStateField
Marc-André Lureau
1
-6
/
+8
2018-11-17
target/mips: Disable R5900 support
Aleksandar Markovic
1
-59
/
+0
2018-11-17
target/mips: Rename MMI-related functions
Aleksandar Markovic
1
-16
/
+16
2018-11-17
target/mips: Rename MMI-related opcodes
Aleksandar Markovic
1
-236
/
+236
2018-11-17
target/mips: Rename MMI-related masks
Aleksandar Markovic
1
-10
/
+10
2018-11-17
target/mips: Guard check_insn with INSN_R5900 check
Fredrik Noring
1
-3
/
+6
2018-11-17
target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
Fredrik Noring
1
-4
/
+12
2018-11-17
target/mips: Fix decoding mechanism of special R5900 opcodes
Fredrik Noring
1
-4
/
+50
2018-11-17
target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
Fredrik Noring
1
-6
/
+59
2018-11-17
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
Fredrik Noring
1
-11
/
+40
2018-10-29
target/mips: Amend MXU ASE overview note
Aleksandar Markovic
1
-10
/
+74
2018-10-29
target/mips: Move MXU_EN check one level higher
Aleksandar Markovic
1
-271
/
+238
2018-10-29
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Craig Janeczek
1
-7
/
+47
2018-10-29
target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Craig Janeczek
1
-7
/
+94
2018-10-29
target/mips: Add emulation of MXU instruction D16MAC
Craig Janeczek
1
-3
/
+87
2018-10-29
target/mips: Add emulation of MXU instruction D16MUL
Craig Janeczek
1
-3
/
+63
2018-10-29
target/mips: Add emulation of MXU instruction S8LDD
Craig Janeczek
1
-3
/
+87
2018-10-29
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Aleksandar Markovic
1
-18
/
+23
2018-10-29
target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Craig Janeczek
1
-6
/
+85
2018-10-29
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Craig Janeczek
1
-1
/
+18
2018-10-29
target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Craig Janeczek
1
-0
/
+10
2018-10-29
target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Craig Janeczek
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Aleksandar Markovic
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Craig Janeczek
1
-0
/
+6
2018-10-29
target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'
Aleksandar Markovic
1
-0
/
+6
2018-10-29
target/mips: Add MXU decoding engine
Aleksandar Markovic
1
-2
/
+1141
2018-10-29
target/mips: Add and integrate MXU decoding engine placeholder
Aleksandar Markovic
1
-0
/
+8
2018-10-29
target/mips: Amend MXU instruction opcodes
Aleksandar Markovic
1
-91
/
+69
2018-10-29
target/mips: Define a bit for MXU in insn_flags
Craig Janeczek
1
-0
/
+1
2018-10-29
target/mips: Introduce MXU registers
Craig Janeczek
2
-0
/
+30
2018-10-29
target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Aleksandar Markovic
1
-0
/
+2
2018-10-25
target/mips: Add disassembler support for nanoMIPS
Aleksandar Markovic
1
-2
/
+11
2018-10-25
target/mips: Implement emulation of nanoMIPS EVA instructions
Dimitrije Nikolic
1
-0
/
+128
2018-10-25
target/mips: Add nanoMIPS CRC32 instruction pool
Aleksandar Markovic
1
-0
/
+10
2018-10-24
target/mips: Fix decoding of ALIGN and DALIGN instructions
Aleksandar Markovic
1
-8
/
+32
2018-10-24
target/mips: Fix the title of translate.c
Aleksandar Markovic
1
-1
/
+1
2018-10-24
target/mips: Define the R5900 CPU
Fredrik Noring
1
-0
/
+59
2018-10-24
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
Fredrik Noring
1
-1
/
+22
2018-10-24
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
Fredrik Noring
1
-2
/
+3
2018-10-24
target/mips: Support R5900 DIV1 and DIVU1 instructions
Fredrik Noring
1
-3
/
+9
2018-10-24
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Fredrik Noring
1
-6
/
+17
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